uart0vhdl.txt

vhdl实现fpga和PC机的简单通信(发送),

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity uart is
port
(
	clk,rst,wrn: in std_logic;
	txd:		 out std_logic	
);
end uart;

architecture behave of uart is

signal sig_clk,tbre,tsre: std_logic ;
signal din:  std_logic_vector(7 downto 0 );
component clk_gen 
	port( 
	 	 clk: in std_logic;
		 clk_out: out std_logic
		);
end component;

component txmit 
	port 
	(
		rst,clk16x,wrn : in std_logic ;
		din : in std_logic_vector(7 downto 0) ;
		tbre : out std_logic ;
		tsre : out std_logic ;
		sdo  : out std_logic 
	);
end component;

begin
	
	u1: clk_gen port map(clk,sig_clk);
	u2: txmit   port map(rst,sig_clk,wrn,din,tbre,tsre,txd); 

p1:process(wrn)					--按键一次din加1并输出
begin
	if rst='1' then	
		if wrn'event and wrn='0' then
		   din<=din+1;
		end if;
	else
		din<="00000000";
	end if;
end process;

end behave;