txd.map.rpt

用verilog实现的串口收发数据程序

; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 16        ;
; Total combinational functions   ; 5         ;
;     -- Total 4-input functions  ; 2         ;
;     -- Total 3-input functions  ; 2         ;
;     -- Total 2-input functions  ; 1         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 15        ;
; I/O pins                        ; 3         ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 15        ;
; Total fan-out                   ; 54        ;
; Average fan-out                 ; 2.84      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |txd                       ; 16 (16)     ; 15           ; 0           ; 3    ; 0            ; 1 (1)        ; 11 (11)           ; 4 (4)            ; 0 (0)           ; |txd                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------+
; State Machine - |txd|n                                                                           ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
; Name   ; n.1001 ; n.0001 ; n.0010 ; n.0011 ; n.0100 ; n.0101 ; n.0110 ; n.0111 ; n.1000 ; n.0000 ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
; n.0000 ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ;
; n.1000 ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 1      ;
; n.0111 ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 1      ;
; n.0110 ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 1      ;
; n.0101 ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 1      ;
; n.0100 ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 1      ;
; n.0011 ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ;
; n.0010 ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ;
; n.0001 ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ;
; n.1001 ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ;
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |txd|num[2]                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/FPGA程序/test_txd/txd.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 05 15:58:45 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off txd -c txd
Info: Found 1 design units, including 1 entities, in source file txd.v
    Info: Found entity 1: txd
Info: Elaborating entity "txd" for the top level hierarchy
Info: State machine "|txd|n" contains 10 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|txd|n"
Info: Encoding result for state machine "|txd|n"
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit "n.1001"
        Info: Encoded state bit "n.0001"
        Info: Encoded state bit "n.0010"
        Info: Encoded state bit "n.0011"
        Info: Encoded state bit "n.0100"
        Info: Encoded state bit "n.0101"
        Info: Encoded state bit "n.0110"
        Info: Encoded state bit "n.0111"
        Info: Encoded state bit "n.1000"
        Info: Encoded state bit "n.0000"
    Info: State "|txd|n.0000" uses code string "0000000000"
    Info: State "|txd|n.1000" uses code string "0000000011"
    Info: State "|txd|n.0111" uses code string "0000000101"
    Info: State "|txd|n.0110" uses code string "0000001001"
    Info: State "|txd|n.0101" uses code string "0000010001"
    Info: State "|txd|n.0100" uses code string "0000100001"
    Info: State "|txd|n.0011" uses code string "0001000001"
    Info: State "|txd|n.0010" uses code string "0010000001"
    Info: State "|txd|n.0001" uses code string "0100000001"
    Info: State "|txd|n.1001" uses code string "1000000001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "vcc" stuck at VCC
Info: Implemented 19 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 2 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Dec 05 15:58:46 2007
    Info: Elapsed time: 00:00:02