txd.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register num\[3\] n.0000 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"num\[3\]\" and destination register \"n.0000\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.726 ns + Longest register register " "Info: + Longest register to register delay is 2.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[3\] 1 REG LC_X10_Y2_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N1; Fanout = 2; REG Node = 'num\[3\]'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { num[3] } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.590 ns) 1.135 ns reduce_nor~19 2 COMB LC_X10_Y2_N8 11 " "Info: 2: + IC(0.545 ns) + CELL(0.590 ns) = 1.135 ns; Loc. = LC_X10_Y2_N8; Fanout = 11; COMB Node = 'reduce_nor~19'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "1.135 ns" { num[3] reduce_nor~19 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.867 ns) 2.726 ns n.0000 3 REG LC_X9_Y2_N6 1 " "Info: 3: + IC(0.724 ns) + CELL(0.867 ns) = 2.726 ns; Loc. = LC_X9_Y2_N6; Fanout = 1; REG Node = 'n.0000'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "1.591 ns" { reduce_nor~19 n.0000 } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 53.45 % " "Info: Total cell delay = 1.457 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns 46.55 % " "Info: Total interconnect delay = 1.269 ns ( 46.55 % )" {  } {  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.726 ns" { num[3] reduce_nor~19 n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.726 ns" { num[3] reduce_nor~19 n.0000 } { 0.000ns 0.545ns 0.724ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { clk } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns n.0000 2 REG LC_X9_Y2_N6 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X9_Y2_N6; Fanout = 1; REG Node = 'n.0000'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "1.434 ns" { clk n.0000 } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 n.0000 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { clk } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns num\[3\] 2 REG LC_X10_Y2_N1 2 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y2_N1; Fanout = 2; REG Node = 'num\[3\]'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "1.434 ns" { clk num[3] } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 num[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 n.0000 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 num[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.726 ns" { num[3] reduce_nor~19 n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.726 ns" { num[3] reduce_nor~19 n.0000 } { 0.000ns 0.545ns 0.724ns } { 0.000ns 0.590ns 0.867ns } } } { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 n.0000 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 num[3] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { n.0000 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { n.0000 } {  } {  } } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd txd~reg0 6.578 ns register " "Info: tco from clock \"clk\" to destination pin \"txd\" through register \"txd~reg0\" is 6.578 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { clk } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns txd~reg0 2 REG LC_X10_Y2_N5 1 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y2_N5; Fanout = 1; REG Node = 'txd~reg0'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "1.434 ns" { clk txd~reg0 } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk txd~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 txd~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.451 ns + Longest register pin " "Info: + Longest register to pin delay is 3.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd~reg0 1 REG LC_X10_Y2_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N5; Fanout = 1; REG Node = 'txd~reg0'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "" { txd~reg0 } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(2.108 ns) 3.451 ns txd 2 PIN PIN_79 0 " "Info: 2: + IC(1.343 ns) + CELL(2.108 ns) = 3.451 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'txd'" {  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "3.451 ns" { txd~reg0 txd } "NODE_NAME" } "" } } { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 61.08 % " "Info: Total cell delay = 2.108 ns ( 61.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.343 ns 38.92 % " "Info: Total interconnect delay = 1.343 ns ( 38.92 % )" {  } {  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "3.451 ns" { txd~reg0 txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.451 ns" { txd~reg0 txd } { 0.000ns 1.343ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "2.903 ns" { clk txd~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 txd~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" "" { Report "F:/FPGA程序/test_txd/db/txd_cmp.qrpt" Compiler "txd" "UNKNOWN" "V1" "F:/FPGA程序/test_txd/db/txd.quartus_db" { Floorplan "F:/FPGA程序/test_txd/" "" "3.451 ns" { txd~reg0 txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.451 ns" { txd~reg0 txd } { 0.000ns 1.343ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 05 15:58:57 2007 " "Info: Processing ended: Wed Dec 05 15:58:57 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}