txd.map.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 05 15:58:45 2007 " "Info: Processing started: Wed Dec 05 15:58:45 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off txd -c txd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off txd -c txd" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file txd.v" { { "Info" "ISGN_ENTITY_NAME" "1 txd " "Info: Found entity 1: txd" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "txd " "Info: Elaborating entity \"txd\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|txd\|n 10 0 " "Info: State machine \"\|txd\|n\" contains 10 states and 0 state bits" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|txd\|n " "Info: Selected Auto state machine encoding method for state machine \"\|txd\|n\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|txd\|n " "Info: Encoding result for state machine \"\|txd\|n\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.1001 " "Info: Encoded state bit \"n.1001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0001 " "Info: Encoded state bit \"n.0001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0010 " "Info: Encoded state bit \"n.0010\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0011 " "Info: Encoded state bit \"n.0011\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0100 " "Info: Encoded state bit \"n.0100\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0101 " "Info: Encoded state bit \"n.0101\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0110 " "Info: Encoded state bit \"n.0110\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0111 " "Info: Encoded state bit \"n.0111\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.1000 " "Info: Encoded state bit \"n.1000\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "n.0000 " "Info: Encoded state bit \"n.0000\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0000 0000000000 " "Info: State \"\|txd\|n.0000\" uses code string \"0000000000\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.1000 0000000011 " "Info: State \"\|txd\|n.1000\" uses code string \"0000000011\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0111 0000000101 " "Info: State \"\|txd\|n.0111\" uses code string \"0000000101\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0110 0000001001 " "Info: State \"\|txd\|n.0110\" uses code string \"0000001001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0101 0000010001 " "Info: State \"\|txd\|n.0101\" uses code string \"0000010001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0100 0000100001 " "Info: State \"\|txd\|n.0100\" uses code string \"0000100001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0011 0001000001 " "Info: State \"\|txd\|n.0011\" uses code string \"0001000001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0010 0010000001 " "Info: State \"\|txd\|n.0010\" uses code string \"0010000001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.0001 0100000001 " "Info: State \"\|txd\|n.0001\" uses code string \"0100000001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|txd\|n.1001 1000000001 " "Info: State \"\|txd\|n.1001\" uses code string \"1000000001\"" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "vcc VCC " "Warning: Pin \"vcc\" stuck at VCC" {  } { { "txd.v" "" { Text "F:/FPGA程序/test_txd/txd.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 05 15:58:46 2007 " "Info: Processing ended: Wed Dec 05 15:58:46 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}