txd.map.eqn

用verilog实现的串口收发数据程序

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--A1L91Q is txd~reg0
--operation mode is normal

A1L91Q_lut_out = n.0110 # n.0101 # n.1001;
A1L91Q = DFFEAS(A1L91Q_lut_out, clk, VCC, , A1L71, , , , );


--n.0110 is n.0110
--operation mode is normal

n.0110_lut_out = n.0101;
n.0110 = DFFEAS(n.0110_lut_out, clk, VCC, , A1L71, , , , );


--n.0101 is n.0101
--operation mode is normal

n.0101_lut_out = n.0100;
n.0101 = DFFEAS(n.0101_lut_out, clk, VCC, , A1L71, , , , );


--n.1001 is n.1001
--operation mode is normal

n.1001_lut_out = n.1000;
n.1001 = DFFEAS(n.1001_lut_out, clk, VCC, , A1L71, , , , );


--num[2] is num[2]
--operation mode is normal

num[2]_lut_out = num[2] $ (num[1] & num[0]);
num[2] = DFFEAS(num[2]_lut_out, clk, VCC, , , , , , );


--num[1] is num[1]
--operation mode is normal

num[1]_lut_out = num[1] $ num[0];
num[1] = DFFEAS(num[1]_lut_out, clk, VCC, , , , , , );


--num[0] is num[0]
--operation mode is normal

num[0]_lut_out = !num[0];
num[0] = DFFEAS(num[0]_lut_out, clk, VCC, , , , , , );


--num[3] is num[3]
--operation mode is normal

num[3]_lut_out = num[3] $ (num[2] & num[1] & num[0]);
num[3] = DFFEAS(num[3]_lut_out, clk, VCC, , , , , , );


--A1L71 is reduce_nor~19
--operation mode is normal

A1L71 = !num[2] & !num[1] & !num[0] & !num[3];


--n.0100 is n.0100
--operation mode is normal

n.0100_lut_out = n.0011;
n.0100 = DFFEAS(n.0100_lut_out, clk, VCC, , A1L71, , , , );


--n.1000 is n.1000
--operation mode is normal

n.1000_lut_out = n.0111;
n.1000 = DFFEAS(n.1000_lut_out, clk, VCC, , A1L71, , , , );


--n.0011 is n.0011
--operation mode is normal

n.0011_lut_out = n.0010;
n.0011 = DFFEAS(n.0011_lut_out, clk, VCC, , A1L71, , , , );


--n.0111 is n.0111
--operation mode is normal

n.0111_lut_out = n.0110;
n.0111 = DFFEAS(n.0111_lut_out, clk, VCC, , A1L71, , , , );


--n.0010 is n.0010
--operation mode is normal

n.0010_lut_out = n.0001;
n.0010 = DFFEAS(n.0010_lut_out, clk, VCC, , A1L71, , , , );


--n.0001 is n.0001
--operation mode is normal

n.0001_lut_out = !n.0000;
n.0001 = DFFEAS(n.0001_lut_out, clk, VCC, , A1L71, , , , );


--n.0000 is n.0000
--operation mode is normal

n.0000_lut_out = !n.1001;
n.0000 = DFFEAS(n.0000_lut_out, clk, VCC, , A1L71, , , , );


--clk is clk
--operation mode is input

clk = INPUT();


--txd is txd
--operation mode is output

txd = OUTPUT(A1L91Q);


--vcc is vcc
--operation mode is output

vcc = OUTPUT(VCC);