📄 did.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 10 23:06:38 2007 " "Info: Processing started: Wed Oct 10 23:06:38 2007" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off did -c did --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off did -c did --timing_analysis_only" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "did.v" "" { Text "F:/did/did.v" 2 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register num\[3\] register num\[5\] 250.63 MHz 3.99 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 250.63 MHz between source register \"num\[3\]\" and destination register \"num\[5\]\" (period= 3.99 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.729 ns + Longest register register " "Info: + Longest register to register delay is 3.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[3\] 1 REG LC_X2_Y17_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = 'num\[3\]'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "" { num[3] } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(0.718 ns) 1.834 ns add~108 2 COMB LC_X2_Y17_N4 2 " "Info: 2: + IC(1.116 ns) + CELL(0.718 ns) = 1.834 ns; Loc. = LC_X2_Y17_N4; Fanout = 2; COMB Node = 'add~108'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "1.834 ns" { num[3] add~108 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.455 ns add~111 3 COMB LC_X2_Y17_N6 1 " "Info: 3: + IC(0.000 ns) + CELL(0.621 ns) = 2.455 ns; Loc. = LC_X2_Y17_N6; Fanout = 1; COMB Node = 'add~111'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "0.621 ns" { add~108 add~111 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.607 ns) 3.729 ns num\[5\] 4 REG LC_X2_Y17_N9 3 " "Info: 4: + IC(0.667 ns) + CELL(0.607 ns) = 3.729 ns; Loc. = LC_X2_Y17_N9; Fanout = 3; REG Node = 'num\[5\]'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "1.274 ns" { add~111 num[5] } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.946 ns 52.19 % " "Info: Total cell delay = 1.946 ns ( 52.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.783 ns 47.81 % " "Info: Total interconnect delay = 1.783 ns ( 47.81 % )" { } { } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "3.729 ns" { num[3] add~108 add~111 num[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.729 ns" { num[3] add~108 add~111 num[5] } { 0.000ns 1.116ns 0.000ns 0.667ns } { 0.000ns 0.718ns 0.621ns 0.607ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "" { CLK } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns num\[5\] 2 REG LC_X2_Y17_N9 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N9; Fanout = 3; REG Node = 'num\[5\]'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "1.485 ns" { CLK num[5] } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "" { CLK } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns num\[3\] 2 REG LC_X2_Y17_N7 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = 'num\[3\]'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "1.485 ns" { CLK num[3] } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[3] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[3] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "did.v" "" { Text "F:/did/did.v" 5 -1 0 } } } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "3.729 ns" { num[3] add~108 add~111 num[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.729 ns" { num[3] add~108 add~111 num[5] } { 0.000ns 1.116ns 0.000ns 0.667ns } { 0.000ns 0.718ns 0.621ns 0.607ns } } } { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK num[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 num[3] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK CLK_OUT CLK_OUT~reg0 6.446 ns register " "Info: tco from clock \"CLK\" to destination pin \"CLK_OUT\" through register \"CLK_OUT~reg0\" is 6.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "" { CLK } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns CLK_OUT~reg0 2 REG LC_X1_Y17_N4 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'CLK_OUT~reg0'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "1.485 ns" { CLK CLK_OUT~reg0 } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 23 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK CLK_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 CLK_OUT~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "did.v" "" { Text "F:/did/did.v" 23 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.268 ns + Longest register pin " "Info: + Longest register to pin delay is 3.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_OUT~reg0 1 REG LC_X1_Y17_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'CLK_OUT~reg0'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "" { CLK_OUT~reg0 } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 23 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(2.124 ns) 3.268 ns CLK_OUT 2 PIN PIN_11 0 " "Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'CLK_OUT'" { } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "3.268 ns" { CLK_OUT~reg0 CLK_OUT } "NODE_NAME" } "" } } { "did.v" "" { Text "F:/did/did.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 64.99 % " "Info: Total cell delay = 2.124 ns ( 64.99 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns 35.01 % " "Info: Total interconnect delay = 1.144 ns ( 35.01 % )" { } { } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "3.268 ns" { CLK_OUT~reg0 CLK_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.268 ns" { CLK_OUT~reg0 CLK_OUT } { 0.000ns 1.144ns } { 0.000ns 2.124ns } } } } 0} } { { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "2.954 ns" { CLK CLK_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 CLK_OUT~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/did/db/did_cmp.qrpt" "" { Report "F:/did/db/did_cmp.qrpt" Compiler "did" "UNKNOWN" "V1" "F:/did/db/did.quartus_db" { Floorplan "F:/did/" "" "3.268 ns" { CLK_OUT~reg0 CLK_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.268 ns" { CLK_OUT~reg0 CLK_OUT } { 0.000ns 1.144ns } { 0.000ns 2.124ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 23:06:39 2007 " "Info: Processing ended: Wed Oct 10 23:06:39 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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