did.fit.eqn

用verilog实现的串口收发数据程序

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--A1L3Q is CLK_OUT~reg0 at LC_X1_Y17_N4
--operation mode is normal

A1L3Q_lut_out = num[5] # num[3] & !A1L4 & num[4];
A1L3Q = DFFEAS(A1L3Q_lut_out, GLOBAL(CLK), VCC, , , , , , );


--num[2] is num[2] at LC_X2_Y17_N0
--operation mode is normal

num[2]_lut_out = A1L5 & (A1L92 # !num[1] # !num[0]);
num[2] = DFFEAS(num[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--A1L4 is LessThan~83 at LC_X1_Y17_N2
--operation mode is normal

num[1]_qfbk = num[1];
A1L4 = !num[2] & !num[1]_qfbk;

--num[1] is num[1] at LC_X1_Y17_N2
--operation mode is normal

num[1] = DFFEAS(A1L4, GLOBAL(CLK), VCC, , , A1L8, , , VCC);


--num[4] is num[4] at LC_X2_Y17_N8
--operation mode is normal

num[4]_lut_out = A1L11 & (A1L92 # !num[1] # !num[0]);
num[4] = DFFEAS(num[4]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--num[5] is num[5] at LC_X2_Y17_N9
--operation mode is normal

num[5]_lut_out = A1L81 & (A1L92 # !num[1] # !num[0]);
num[5] = DFFEAS(num[5]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--A1L5 is add~91 at LC_X2_Y17_N3
--operation mode is arithmetic

A1L5 = num[2] $ !A1L9;

--A1L6 is add~93 at LC_X2_Y17_N3
--operation mode is arithmetic

A1L6_cout_0 = num[2] & !A1L9;
A1L6 = CARRY(A1L6_cout_0);

--A1L7 is add~93COUT1 at LC_X2_Y17_N3
--operation mode is arithmetic

A1L7_cout_1 = num[2] & !A1L01;
A1L7 = CARRY(A1L7_cout_1);


--A1L92 is reduce_nor~28 at LC_X2_Y17_N7
--operation mode is normal

num[3]_qfbk = num[3];
A1L92 = num[3]_qfbk # num[2] # !num[4] # !num[5];

--num[3] is num[3] at LC_X2_Y17_N7
--operation mode is normal

num[3] = DFFEAS(A1L92, GLOBAL(CLK), VCC, , , A1L41, , , VCC);


--num[0] is num[0] at LC_X3_Y17_N2
--operation mode is normal

num[0]_lut_out = A1L91;
num[0] = DFFEAS(num[0]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--A1L8 is add~96 at LC_X2_Y17_N2
--operation mode is arithmetic

A1L8 = num[1] $ A1L02;

--A1L9 is add~98 at LC_X2_Y17_N2
--operation mode is arithmetic

A1L9_cout_0 = !A1L02 # !num[1];
A1L9 = CARRY(A1L9_cout_0);

--A1L01 is add~98COUT1_123 at LC_X2_Y17_N2
--operation mode is arithmetic

A1L01_cout_1 = !A1L12 # !num[1];
A1L01 = CARRY(A1L01_cout_1);


--A1L11 is add~101 at LC_X2_Y17_N5
--operation mode is arithmetic

A1L11_carry_eqn = (!A1L51 & GND) # (A1L51 & VCC);
A1L11 = num[4] $ !A1L11_carry_eqn;

--A1L21 is add~103 at LC_X2_Y17_N5
--operation mode is arithmetic

A1L21_cout_0 = num[4] & !A1L51;
A1L21 = CARRY(A1L21_cout_0);

--A1L31 is add~103COUT1_124 at LC_X2_Y17_N5
--operation mode is arithmetic

A1L31_cout_1 = num[4] & !A1L51;
A1L31 = CARRY(A1L31_cout_1);


--A1L41 is add~106 at LC_X2_Y17_N4
--operation mode is arithmetic

A1L41 = num[3] $ (A1L6);

--A1L51 is add~108 at LC_X2_Y17_N4
--operation mode is arithmetic

A1L51 = A1L61;


--A1L81 is add~111 at LC_X2_Y17_N6
--operation mode is normal

A1L81_carry_eqn = (!A1L51 & A1L21) # (A1L51 & A1L31);
A1L81 = num[5] $ (A1L81_carry_eqn);


--A1L91 is add~116 at LC_X2_Y17_N1
--operation mode is arithmetic

A1L91 = !num[0];

--A1L02 is add~118 at LC_X2_Y17_N1
--operation mode is arithmetic

A1L02_cout_0 = num[0];
A1L02 = CARRY(A1L02_cout_0);

--A1L12 is add~118COUT1_122 at LC_X2_Y17_N1
--operation mode is arithmetic

A1L12_cout_1 = num[0];
A1L12 = CARRY(A1L12_cout_1);


--CLK is CLK at PIN_29
--operation mode is input

CLK = INPUT();


--CLK_OUT is CLK_OUT at PIN_11
--operation mode is output

CLK_OUT = OUTPUT(A1L3Q);