did.fit.rpt

用verilog实现的串口收发数据程序

; 1                                          ; 1                           ;
; 2                                          ; 1                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 1                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 3) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 3                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 5.00) ; Number of LABs  (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 1                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 3.00) ; Number of LABs  (Total = 3) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
; 2                                               ; 1                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 3.67) ; Number of LABs  (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
; 3                                           ; 1                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Oct 10 23:06:30 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off did -c did
Info: Selected device EP1C6Q240C8 for design "did"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C12Q240C8 is compatible
Info: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin CLK_OUT not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "CLK" to use Global clock in PIN 29
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.180 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y17; Fanout = 6; REG Node = 'num[0]'
    Info: 2: + IC(0.696 ns) + CELL(0.575 ns) = 1.271 ns; Loc. = LAB_X2_Y17; Fanout = 2; COMB Node = 'add~118COUT1_122'
    Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.351 ns; Loc. = LAB_X2_Y17; Fanout = 2; COMB Node = 'add~98COUT1_123'
    Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.431 ns; Loc. = LAB_X2_Y17; Fanout = 2; COMB Node = 'add~93COUT1'
    Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.689 ns; Loc. = LAB_X2_Y17; Fanout = 2; COMB Node = 'add~108'
    Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.368 ns; Loc. = LAB_X2_Y17; Fanout = 1; COMB Node = 'add~111'
    Info: 7: + IC(0.074 ns) + CELL(0.738 ns) = 3.180 ns; Loc. = LAB_X2_Y17; Fanout = 3; REG Node = 'num[5]'
    Info: Total cell delay = 2.410 ns ( 75.79 % )
    Info: Total interconnect delay = 0.770 ns ( 24.21 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Oct 10 23:06:34 2007
    Info: Elapsed time: 00:00:04