did.tan.rpt

用verilog实现的串口收发数据程序

; N/A   ; 267.31 MHz ( period = 3.741 ns )               ; num[3] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 3.480 ns                ;
; N/A   ; 275.03 MHz ( period = 3.636 ns )               ; num[1] ; num[5]       ; CLK        ; CLK      ; None                        ; None                      ; 3.375 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 3.361 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 3.126 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 3.105 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[5]       ; CLK        ; CLK      ; None                        ; None                      ; 3.023 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 2.866 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[5]       ; CLK        ; CLK      ; None                        ; None                      ; 2.833 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[1]       ; CLK        ; CLK      ; None                        ; None                      ; 2.821 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 2.774 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[3]       ; CLK        ; CLK      ; None                        ; None                      ; 2.728 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[3]       ; CLK        ; CLK      ; None                        ; None                      ; 2.489 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[5]       ; CLK        ; CLK      ; None                        ; None                      ; 2.415 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[0]       ; CLK        ; CLK      ; None                        ; None                      ; 2.398 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[3]       ; CLK        ; CLK      ; None                        ; None                      ; 2.274 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[3]       ; CLK        ; CLK      ; None                        ; None                      ; 2.135 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 2.097 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 2.093 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; CLK_OUT~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.081 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[1]       ; CLK        ; CLK      ; None                        ; None                      ; 2.064 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 1.994 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[4]       ; CLK        ; CLK      ; None                        ; None                      ; 1.986 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 1.916 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; CLK_OUT~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 1.496 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[4] ; CLK_OUT~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 1.426 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[5] ; CLK_OUT~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 1.337 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[2]       ; CLK        ; CLK      ; None                        ; None                      ; 1.334 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; CLK_OUT~reg0 ; CLK        ; CLK      ; None                        ; None                      ; 1.293 ns                ;
+-------+------------------------------------------------+--------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.446 ns   ; CLK_OUT~reg0 ; CLK_OUT ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Oct 10 23:06:38 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off did -c did --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 250.63 MHz between source register "num[3]" and destination register "num[5]" (period= 3.99 ns)
    Info: + Longest register to register delay is 3.729 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = 'num[3]'
        Info: 2: + IC(1.116 ns) + CELL(0.718 ns) = 1.834 ns; Loc. = LC_X2_Y17_N4; Fanout = 2; COMB Node = 'add~108'
        Info: 3: + IC(0.000 ns) + CELL(0.621 ns) = 2.455 ns; Loc. = LC_X2_Y17_N6; Fanout = 1; COMB Node = 'add~111'
        Info: 4: + IC(0.667 ns) + CELL(0.607 ns) = 3.729 ns; Loc. = LC_X2_Y17_N9; Fanout = 3; REG Node = 'num[5]'
        Info: Total cell delay = 1.946 ns ( 52.19 % )
        Info: Total interconnect delay = 1.783 ns ( 47.81 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N9; Fanout = 3; REG Node = 'num[5]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = 'num[3]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "CLK_OUT" through register "CLK_OUT~reg0" is 6.446 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'CLK_OUT~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.268 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'CLK_OUT~reg0'
        Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'CLK_OUT'
        Info: Total cell delay = 2.124 ns ( 64.99 % )
        Info: Total interconnect delay = 1.144 ns ( 35.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Oct 10 23:06:39 2007
    Info: Elapsed time: 00:00:01