sent.map.summary

用verilog实现的串口收发数据程序

Flow Status : Successful - Fri Dec 14 23:26:38 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : sent
Top-level Entity Name : sent
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 335
Total pins : 7
Total virtual pins : 0
Total memory bits : 8,192
Total PLLs : 0