sent.map.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_re92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_re92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_re92 " "Info: Found entity 1: altsyncram_re92" {  } { { "db/altsyncram_re92.tdf" "" { Text "F:/复件 FPGA程序/sent/db/altsyncram_re92.tdf" 38 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_fga.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_fga.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_fga " "Info: Found entity 1: decode_fga" {  } { { "db/decode_fga.tdf" "" { Text "F:/复件 FPGA程序/sent/db/decode_fga.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_oab.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_oab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_oab " "Info: Found entity 1: mux_oab" {  } { { "db/mux_oab.tdf" "" { Text "F:/复件 FPGA程序/sent/db/mux_oab.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tn7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_tn7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tn7 " "Info: Found entity 1: cntr_tn7" {  } { { "db/cntr_tn7.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_tn7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "sent " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"sent\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sent\|CLK acq_clk " "Info: Source node \"\|sent\|CLK\" connects to port \"acq_clk\"" {  } { { "sent.bdf" "CLK" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sent\|txd acq_trigger_in\[0\] " "Info: Source node \"\|sent\|txd\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "sent.bdf" "txd" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 416 592 104 "txd" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sent\|txd acq_data_in\[0\] " "Info: Source node \"\|sent\|txd\" connects to port \"acq_data_in\[0\]\"" {  } { { "sent.bdf" "txd" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 416 592 104 "txd" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "F:/复件 FPGA程序/sent/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|sent\|txd:inst2\|n 10 0 " "Info: State machine \"\|sent\|txd:inst2\|n\" contains 10 states and 0 state bits" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|sent\|txd:inst2\|n " "Info: Selected Auto state machine encoding method for state machine \"\|sent\|txd:inst2\|n\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|sent\|txd:inst2\|n " "Info: Encoding result for state machine \"\|sent\|txd:inst2\|n\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.1001 " "Info: Encoded state bit \"txd:inst2\|n.1001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0001 " "Info: Encoded state bit \"txd:inst2\|n.0001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0010 " "Info: Encoded state bit \"txd:inst2\|n.0010\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0011 " "Info: Encoded state bit \"txd:inst2\|n.0011\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0100 " "Info: Encoded state bit \"txd:inst2\|n.0100\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0101 " "Info: Encoded state bit \"txd:inst2\|n.0101\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0110 " "Info: Encoded state bit \"txd:inst2\|n.0110\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0111 " "Info: Encoded state bit \"txd:inst2\|n.0111\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.1000 " "Info: Encoded state bit \"txd:inst2\|n.1000\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst2\|n.0000 " "Info: Encoded state bit \"txd:inst2\|n.0000\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0000 0000000000 " "Info: State \"\|sent\|txd:inst2\|n.0000\" uses code string \"0000000000\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.1000 0000000011 " "Info: State \"\|sent\|txd:inst2\|n.1000\" uses code string \"0000000011\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0111 0000000101 " "Info: State \"\|sent\|txd:inst2\|n.0111\" uses code string \"0000000101\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0110 0000001001 " "Info: State \"\|sent\|txd:inst2\|n.0110\" uses code string \"0000001001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0101 0000010001 " "Info: State \"\|sent\|txd:inst2\|n.0101\" uses code string \"0000010001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0100 0000100001 " "Info: State \"\|sent\|txd:inst2\|n.0100\" uses code string \"0000100001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0011 0001000001 " "Info: State \"\|sent\|txd:inst2\|n.0011\" uses code string \"0001000001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0010 0010000001 " "Info: State \"\|sent\|txd:inst2\|n.0010\" uses code string \"0010000001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.0001 0100000001 " "Info: State \"\|sent\|txd:inst2\|n.0001\" uses code string \"0100000001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|sent\|txd:inst2\|n.1001 1000000001 " "Info: State \"\|sent\|txd:inst2\|n.1001\" uses code string \"1000000001\"" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 7 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "10 " "Info: Ignored 10 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "10 " "Info: Ignored 10 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:sent\|acq_data_in_reg\[0\] sld_signaltap:sent\|acq_trigger_in_reg\[0\] " "Info: Duplicate register \"sld_signaltap:sent\|acq_data_in_reg\[0\]\" merged to single register \"sld_signaltap:sent\|acq_trigger_in_reg\[0\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:sent\|acq_data_in_pipe_reg\[1\]\[0\] sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:sent\|acq_data_in_pipe_reg\[1\]\[0\]\" merged to single register \"sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "vcc VCC " "Warning: Pin \"vcc\" stuck at VCC" {  } { { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 104 416 592 120 "vcc" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "345 " "Info: Implemented 345 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "335 " "Info: Implemented 335 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "2 " "Info: Implemented 2 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:26:37 2007 " "Info: Processing ended: Fri Dec 14 23:26:37 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Info: Elapsed time: 00:00:39" {  } {  } 0}  } {  } 0}