sent.map.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 14 23:25:58 2007 " "Info: Processing started: Fri Dec 14 23:25:58 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sent -c sent " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sent -c sent" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../test_txd/txd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../test_txd/txd.v" { { "Info" "ISGN_ENTITY_NAME" "1 txd " "Info: Found entity 1: txd" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../did/did.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../did/did.v" { { "Info" "ISGN_ENTITY_NAME" "1 did " "Info: Found entity 1: did" {  } { { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sent.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sent.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sent " "Info: Found entity 1: sent" {  } { { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sent " "Info: Elaborating entity \"sent\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "txd txd:inst2 " "Info: Elaborating entity \"txd\" for hierarchy \"txd:inst2\"" {  } { { "sent.bdf" "inst2" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 64 320 416 160 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "did did:inst " "Info: Elaborating entity \"did\" for hierarchy \"did:inst\"" {  } { { "sent.bdf" "inst" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 64 136 264 160 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 118 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_level_seq_mgr-rtl " "Info: Found design unit 2: sld_ela_level_seq_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 844 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_ela_state_machine-rtl " "Info: Found design unit 3: sld_ela_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1022 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_ela_seg_state_machine-rtl " "Info: Found design unit 4: sld_ela_seg_state_machine-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1125 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_ela_post_trigger_counter-rtl " "Info: Found design unit 5: sld_ela_post_trigger_counter-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1215 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 sld_ela_segment_mgr-rtl " "Info: Found design unit 6: sld_ela_segment_mgr-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1342 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 67 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_level_seq_mgr " "Info: Found entity 2: sld_ela_level_seq_mgr" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 817 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 sld_ela_state_machine " "Info: Found entity 3: sld_ela_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1000 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 sld_ela_seg_state_machine " "Info: Found entity 4: sld_ela_seg_state_machine" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1105 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 sld_ela_post_trigger_counter " "Info: Found entity 5: sld_ela_post_trigger_counter" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1195 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 sld_ela_segment_mgr " "Info: Found entity 6: sld_ela_segment_mgr" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1319 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 sld_ela_basic_multi_level_trigger " "Info: Found entity 7: sld_ela_basic_multi_level_trigger" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1487 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 293 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 272 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_po8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_po8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_po8 " "Info: Found entity 1: cntr_po8" {  } { { "db/cntr_po8.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_po8.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_h29.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_h29.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_h29 " "Info: Found entity 1: cntr_h29" {  } { { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7u9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_7u9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7u9 " "Info: Found entity 1: cntr_7u9" {  } { { "db/cntr_7u9.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_7u9.tdf" 25 1 0 } }  } 0}  } {  } 0}