📄 mux_oab.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 1
SUBDESIGN mux_oab
(
data[1..0] : input;
result[0..0] : output;
sel[0..0] : input;
)
VARIABLE
result_node[0..0] : WIRE;
sel_node[0..0] : WIRE;
w_data37w[1..0] : WIRE;
w_result38w : WIRE;
w_result45w : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( w_result38w);
sel_node[] = ( sel[0..0]);
w_data37w[] = ( data[1..0]);
w_result38w = w_result45w;
w_result45w = ((sel_node[] & w_data37w[1..1]) # ((! sel_node[]) & w_data37w[0..0]));
END;
--VALID FILE
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