sent.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] altera_internal_jtag altera_internal_jtag~TCKUTAP 2.599 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.599 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.289 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 171 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 171; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.578 ns) + CELL(0.711 ns) 5.289 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 2 REG LC_X20_Y9_N0 7 " "Info: 2: + IC(4.578 ns) + CELL(0.711 ns) = 5.289 ns; Loc. = LC_X20_Y9_N0; Fanout = 7; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.578 ns 86.56 % " "Info: Total interconnect delay = 4.578 ns ( 86.56 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 4.578ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.705 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y10_N1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 8; PIN Node = 'altera_internal_jtag'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.590 ns) + CELL(0.115 ns) 2.705 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] 2 REG LC_X20_Y9_N0 7 " "Info: 2: + IC(2.590 ns) + CELL(0.115 ns) = 2.705 ns; Loc. = LC_X20_Y9_N0; Fanout = 7; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.705 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 4.25 % " "Info: Total cell delay = 0.115 ns ( 4.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.590 ns 95.75 % " "Info: Total interconnect delay = 2.590 ns ( 95.75 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.705 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.705 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 2.590ns } { 0.000ns 0.115ns } } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 4.578ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.705 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.705 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } { 0.000ns 2.590ns } { 0.000ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:27:19 2007 " "Info: Processing ended: Fri Dec 14 23:27:19 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}