sent.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo 104.56 MHz 9.564 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 104.56 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 9.564 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.510 ns + Longest register register " "Info: + Longest register to register delay is 4.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LC_X16_Y10_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y10_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.617 ns) + CELL(0.442 ns) 2.059 ns sld_hub:sld_hub_inst\|hub_tdo~295 2 COMB LC_X21_Y10_N4 1 " "Info: 2: + IC(1.617 ns) + CELL(0.442 ns) = 2.059 ns; Loc. = LC_X21_Y10_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~295'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.059 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~295 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.292 ns) 3.583 ns sld_hub:sld_hub_inst\|hub_tdo~296 3 COMB LC_X20_Y9_N8 1 " "Info: 3: + IC(1.232 ns) + CELL(0.292 ns) = 3.583 ns; Loc. = LC_X20_Y9_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~296'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.524 ns" { sld_hub:sld_hub_inst|hub_tdo~295 sld_hub:sld_hub_inst|hub_tdo~296 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.478 ns) 4.510 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X20_Y9_N5 0 " "Info: 4: + IC(0.449 ns) + CELL(0.478 ns) = 4.510 ns; Loc. = LC_X20_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "0.927 ns" { sld_hub:sld_hub_inst|hub_tdo~296 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.212 ns 26.87 % " "Info: Total cell delay = 1.212 ns ( 26.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.298 ns 73.13 % " "Info: Total interconnect delay = 3.298 ns ( 73.13 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "4.510 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~295 sld_hub:sld_hub_inst|hub_tdo~296 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.510 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~295 sld_hub:sld_hub_inst|hub_tdo~296 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.617ns 1.232ns 0.449ns } { 0.000ns 0.442ns 0.292ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.289 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 171 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 171; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.578 ns) + CELL(0.711 ns) 5.289 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X20_Y9_N5 0 " "Info: 2: + IC(4.578 ns) + CELL(0.711 ns) = 5.289 ns; Loc. = LC_X20_Y9_N5; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.578 ns 86.56 % " "Info: Total interconnect delay = 4.578 ns ( 86.56 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.578ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 171 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 171; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.589 ns) + CELL(0.711 ns) 5.300 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 2 REG LC_X16_Y10_N4 1 " "Info: 2: + IC(4.589 ns) + CELL(0.711 ns) = 5.300 ns; Loc. = LC_X16_Y10_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.42 % " "Info: Total cell delay = 0.711 ns ( 13.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.589 ns 86.58 % " "Info: Total interconnect delay = 4.589 ns ( 86.58 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.589ns } { 0.000ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.578ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.589ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "4.510 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~295 sld_hub:sld_hub_inst|hub_tdo~296 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.510 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~295 sld_hub:sld_hub_inst|hub_tdo~296 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.617ns 1.232ns 0.449ns } { 0.000ns 0.442ns 0.292ns 0.478ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.289 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.578ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.300 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 4.589ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 0.356 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 0.356 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.637 ns + Longest pin register " "Info: + Longest pin to register delay is 5.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.926 ns) + CELL(0.590 ns) 3.516 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LC_X20_Y9_N4 2 " "Info: 2: + IC(2.926 ns) + CELL(0.590 ns) = 3.516 ns; Loc. = LC_X20_Y9_N4; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "3.516 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 371 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.867 ns) 5.637 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LC_X21_Y11_N9 3 " "Info: 3: + IC(1.254 ns) + CELL(0.867 ns) = 5.637 ns; Loc. = LC_X21_Y11_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.121 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 25.85 % " "Info: Total cell delay = 1.457 ns ( 25.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.180 ns 74.15 % " "Info: Total interconnect delay = 4.180 ns ( 74.15 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.637 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.637 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 2.926ns 1.254ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.318 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 171 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 171; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.607 ns) + CELL(0.711 ns) 5.318 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 2 REG LC_X21_Y11_N9 3 " "Info: 2: + IC(4.607 ns) + CELL(0.711 ns) = 5.318 ns; Loc. = LC_X21_Y11_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.318 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.37 % " "Info: Total cell delay = 0.711 ns ( 13.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.607 ns 86.63 % " "Info: Total interconnect delay = 4.607 ns ( 86.63 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.318 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.318 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.607ns } { 0.000ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.637 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.637 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 2.926ns 1.254ns } { 0.000ns 0.590ns 0.867ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.318 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.318 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.607ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK txd txd:inst2\|txd 12.748 ns register " "Info: tco from clock \"CLK\" to destination pin \"txd\" through register \"txd:inst2\|txd\" is 12.748 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.352 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 101; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { CLK } "NODE_NAME" } "" } } { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns did:inst\|CLK_OUT 2 REG LC_X8_Y10_N5 15 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N5; Fanout = 15; REG Node = 'did:inst\|CLK_OUT'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.680 ns" { CLK did:inst|CLK_OUT } "NODE_NAME" } "" } } { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.492 ns) + CELL(0.711 ns) 7.352 ns txd:inst2\|txd 3 REG LC_X13_Y9_N9 2 " "Info: 3: + IC(3.492 ns) + CELL(0.711 ns) = 7.352 ns; Loc. = LC_X13_Y9_N9; Fanout = 2; REG Node = 'txd:inst2\|txd'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "4.203 ns" { did:inst|CLK_OUT txd:inst2|txd } "NODE_NAME" } "" } } { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.37 % " "Info: Total cell delay = 3.115 ns ( 42.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.237 ns 57.63 % " "Info: Total interconnect delay = 4.237 ns ( 57.63 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "7.352 ns" { CLK did:inst|CLK_OUT txd:inst2|txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.352 ns" { CLK CLK~out0 did:inst|CLK_OUT txd:inst2|txd } { 0.000ns 0.000ns 0.745ns 3.492ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.172 ns + Longest register pin " "Info: + Longest register to pin delay is 5.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd:inst2\|txd 1 REG LC_X13_Y9_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y9_N9; Fanout = 2; REG Node = 'txd:inst2\|txd'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { txd:inst2|txd } "NODE_NAME" } "" } } { "../test_txd/txd.v" "" { Text "F:/复件 FPGA程序/test_txd/txd.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.064 ns) + CELL(2.108 ns) 5.172 ns txd 2 PIN PIN_95 0 " "Info: 2: + IC(3.064 ns) + CELL(2.108 ns) = 5.172 ns; Loc. = PIN_95; Fanout = 0; PIN Node = 'txd'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.172 ns" { txd:inst2|txd txd } "NODE_NAME" } "" } } { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 416 592 104 "txd" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 40.76 % " "Info: Total cell delay = 2.108 ns ( 40.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.064 ns 59.24 % " "Info: Total interconnect delay = 3.064 ns ( 59.24 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.172 ns" { txd:inst2|txd txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.172 ns" { txd:inst2|txd txd } { 0.000ns 3.064ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "7.352 ns" { CLK did:inst|CLK_OUT txd:inst2|txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.352 ns" { CLK CLK~out0 did:inst|CLK_OUT txd:inst2|txd } { 0.000ns 0.000ns 0.745ns 3.492ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "5.172 ns" { txd:inst2|txd txd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.172 ns" { txd:inst2|txd txd } { 0.000ns 3.064ns } { 0.000ns 2.108ns } } }  } 0}