sent.tan.qmsg

用verilog实现的串口收发数据程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "did:inst\|CLK_OUT " "Info: Detected ripple clock \"did:inst\|CLK_OUT\" as buffer" {  } { { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "did:inst\|CLK_OUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\] register sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\] 95.0 MHz 10.526 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 95.0 MHz between source register \"sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\]\" and destination register \"sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\]\" (period= 10.526 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.265 ns + Longest register register " "Info: + Longest register to register delay is 10.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\] 1 REG LC_X26_Y9_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N4; Fanout = 3; REG Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.590 ns) 2.790 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~96 2 COMB LC_X25_Y9_N9 1 " "Info: 2: + IC(2.200 ns) + CELL(0.590 ns) = 2.790 ns; Loc. = LC_X25_Y9_N9; Fanout = 1; COMB Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~96'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.790 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.310 ns) + CELL(0.590 ns) 5.690 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~97 3 COMB LC_X25_Y9_N7 1 " "Info: 3: + IC(2.310 ns) + CELL(0.590 ns) = 5.690 ns; Loc. = LC_X25_Y9_N7; Fanout = 1; COMB Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~97'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.900 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.548 ns) + CELL(0.590 ns) 7.828 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0 4 COMB LC_X26_Y8_N9 14 " "Info: 4: + IC(1.548 ns) + CELL(0.590 ns) = 7.828 ns; Loc. = LC_X26_Y8_N9; Fanout = 14; COMB Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.138 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(1.112 ns) 10.265 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\] 5 REG LC_X26_Y9_N8 4 " "Info: 5: + IC(1.325 ns) + CELL(1.112 ns) = 10.265 ns; Loc. = LC_X26_Y9_N8; Fanout = 4; REG Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.437 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.882 ns 28.08 % " "Info: Total cell delay = 2.882 ns ( 28.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.383 ns 71.92 % " "Info: Total interconnect delay = 7.383 ns ( 71.92 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "10.265 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.265 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } { 0.000ns 2.200ns 2.310ns 1.548ns 1.325ns } { 0.000ns 0.590ns 0.590ns 0.590ns 1.112ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.913 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 101; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { CLK } "NODE_NAME" } "" } } { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.711 ns) 2.913 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\] 2 REG LC_X26_Y9_N8 4 " "Info: 2: + IC(0.733 ns) + CELL(0.711 ns) = 2.913 ns; Loc. = LC_X26_Y9_N8; Fanout = 4; REG Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[4\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.444 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.84 % " "Info: Total cell delay = 2.180 ns ( 74.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.733 ns 25.16 % " "Info: Total interconnect delay = 0.733 ns ( 25.16 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.913 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 101; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { CLK } "NODE_NAME" } "" } } { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.711 ns) 2.913 ns sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\] 2 REG LC_X26_Y9_N4 3 " "Info: 2: + IC(0.733 ns) + CELL(0.711 ns) = 2.913 ns; Loc. = LC_X26_Y9_N4; Fanout = 3; REG Node = 'sld_signaltap:sent\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_h29:auto_generated\|safe_q\[0\]'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.444 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.84 % " "Info: Total cell delay = 2.180 ns ( 74.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.733 ns 25.16 % " "Info: Total interconnect delay = 0.733 ns ( 25.16 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_h29.tdf" "" { Text "F:/复件 FPGA程序/sent/db/cntr_h29.tdf" 144 8 0 } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "10.265 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.265 ns" { sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~96 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~97 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } { 0.000ns 2.200ns 2.310ns 1.548ns 1.325ns } { 0.000ns 0.590ns 0.590ns 0.590ns 1.112ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "2.913 ns" { CLK sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.913 ns" { CLK CLK~out0 sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}