sent.map.rpt

用verilog实现的串口收发数据程序

; sld_node_crc_loword         ; 42349         ; Untyped               ;
; sld_incremental_routing     ; 0             ; Integer               ;
; sld_sample_depth            ; 8192          ; Untyped               ;
; sld_mem_address_bits        ; 13            ; Untyped               ;
; sld_ram_block_type          ; AUTO          ; String                ;
; sld_trigger_level           ; 1             ; Untyped               ;
; sld_trigger_in_enabled      ; 0             ; Untyped               ;
; sld_advanced_trigger_entity ; basic,1,      ; Untyped               ;
; sld_trigger_level_pipeline  ; 1             ; Untyped               ;
; sld_enable_advanced_trigger ; 0             ; Untyped               ;
; sld_advanced_trigger_1      ; NONE          ; String                ;
; sld_advanced_trigger_2      ; NONE          ; String                ;
; sld_advanced_trigger_3      ; NONE          ; String                ;
; sld_advanced_trigger_4      ; NONE          ; String                ;
; sld_advanced_trigger_5      ; NONE          ; String                ;
; sld_advanced_trigger_6      ; NONE          ; String                ;
; sld_advanced_trigger_7      ; NONE          ; String                ;
; sld_advanced_trigger_8      ; NONE          ; String                ;
; sld_advanced_trigger_9      ; NONE          ; String                ;
; sld_advanced_trigger_10     ; NONE          ; String                ;
+-----------------------------+---------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 2                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone                          ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 7                                ; Untyped ;
; node_info                ; 00011000000000000110111000000000 ; Binary  ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                          ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+
; 0              ; sent          ; 1                   ; 1                ; 8192         ; 1              ; 0                       ; no              ; no               ; 0                          ; 0                       ;
+----------------+---------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+----------------------------+-------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/复件 FPGA程序/sent/sent.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Dec 14 23:25:58 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sent -c sent
Info: Found 1 design units, including 1 entities, in source file ../test_txd/txd.v
    Info: Found entity 1: txd
Info: Found 1 design units, including 1 entities, in source file ../did/did.v
    Info: Found entity 1: did
Info: Found 1 design units, including 1 entities, in source file sent.bdf
    Info: Found entity 1: sent
Info: Elaborating entity "sent" for the top level hierarchy
Info: Elaborating entity "txd" for hierarchy "txd:inst2"
Info: Elaborating entity "did" for hierarchy "did:inst"
Info: Found 3 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Found 14 design units, including 7 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigge