sent.fit.rpt

用verilog实现的串口收发数据程序

; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in F:/复件 FPGA程序/sent/sent.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/复件 FPGA程序/sent/sent.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 306 / 5,980 ( 5 % )      ;
;     -- Combinational with no register       ; 71                       ;
;     -- Register only                        ; 51                       ;
;     -- Combinational with a register        ; 184                      ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 98                       ;
;     -- 3 input functions                    ; 60                       ;
;     -- 2 input functions                    ; 82                       ;
;     -- 1 input functions                    ; 30                       ;
;     -- 0 input functions                    ; 36                       ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 248                      ;
;     -- arithmetic mode                      ; 58                       ;
;     -- qfbk mode                            ; 27                       ;
;     -- register cascade mode                ; 0                        ;
;     -- synchronous clear/load mode          ; 88                       ;
;     -- asynchronous clear/load mode         ; 186                      ;
;                                             ;                          ;
; Total LABs                                  ; 40 / 598 ( 6 % )         ;
; Logic elements in carry chains              ; 64                       ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 3 / 185 ( 1 % )          ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )           ;
; Global signals                              ; 8                        ;
; M4Ks                                        ; 2 / 20 ( 10 % )          ;
; Total memory bits                           ; 8,192 / 92,160 ( 8 % )   ;
; Total RAM block bits                        ; 9,216 / 92,160 ( 10 % )  ;
; Global clocks                               ; 8 / 8 ( 100 % )          ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 155                      ;
; Total fan-out                               ; 1472                     ;
; Average fan-out                             ; 4.63                     ;
+---------------------------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLK  ; 152   ; 3        ; 35           ; 12           ; 2           ; 75                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                   ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load        ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; txd  ; 95    ; 4        ; 20           ; 0            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;
; vcc  ; 103   ; 4        ; 26           ; 0            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 2 / 44 ( 4 % ) ; 3.3V          ; --           ;