rec.map.eqn

用verilog实现的串口收发数据程序

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--C1_data_out[7] is test_rec:inst1|data_out[7]
--operation mode is normal

C1_data_out[7]_lut_out = rxd;
C1_data_out[7] = DFFEAS(C1_data_out[7]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[6] is test_rec:inst1|data_out[6]
--operation mode is normal

C1_data_out[6]_lut_out = C1_data_out[7];
C1_data_out[6] = DFFEAS(C1_data_out[6]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[5] is test_rec:inst1|data_out[5]
--operation mode is normal

C1_data_out[5]_lut_out = C1_data_out[6];
C1_data_out[5] = DFFEAS(C1_data_out[5]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[4] is test_rec:inst1|data_out[4]
--operation mode is normal

C1_data_out[4]_lut_out = C1_data_out[5];
C1_data_out[4] = DFFEAS(C1_data_out[4]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[3] is test_rec:inst1|data_out[3]
--operation mode is normal

C1_data_out[3]_lut_out = C1_data_out[4];
C1_data_out[3] = DFFEAS(C1_data_out[3]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[2] is test_rec:inst1|data_out[2]
--operation mode is normal

C1_data_out[2]_lut_out = C1_data_out[3];
C1_data_out[2] = DFFEAS(C1_data_out[2]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[1] is test_rec:inst1|data_out[1]
--operation mode is normal

C1_data_out[1]_lut_out = C1_data_out[2];
C1_data_out[1] = DFFEAS(C1_data_out[1]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_data_out[0] is test_rec:inst1|data_out[0]
--operation mode is normal

C1_data_out[0]_lut_out = C1_data_out[1];
C1_data_out[0] = DFFEAS(C1_data_out[0]_lut_out, B1_CLK_OUT, VCC, , C1L32, , , , );


--C1_state[1] is test_rec:inst1|state[1]
--operation mode is normal

C1_state[1]_lut_out = C1_state[1] $ (!C1L05 & !C1L74 & !C1L84);
C1_state[1] = DFFEAS(C1_state[1]_lut_out, B1_CLK_OUT, VCC, , , , , , );


--C1_state[0] is test_rec:inst1|state[0]
--operation mode is normal

C1_state[0]_lut_out = C1L74 & (!C1L05) # !C1L74 & (C1L84 & (!C1L05) # !C1L84 & C1L22);
C1_state[0] = DFFEAS(C1_state[0]_lut_out, B1_CLK_OUT, VCC, , , , , , );


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !E1_hub_tdo);


--B1_CLK_OUT is did:inst|CLK_OUT
--operation mode is normal

B1_CLK_OUT_lut_out = B1_num[5] # !B1L2 & B1_num[4] & B1_num[3];
B1_CLK_OUT = DFFEAS(B1_CLK_OUT_lut_out, CLK, VCC, , , , , , );


--C1_num[3] is test_rec:inst1|num[3]
--operation mode is normal

C1_num[3]_lut_out = C1L1 & (C1_num[3] & (!C1L44) # !C1_num[3] & C1L05 & C1L44);
C1_num[3] = DFFEAS(C1_num[3]_lut_out, B1_CLK_OUT, VCC, , C1L63, , , , );


--C1_num[2] is test_rec:inst1|num[2]
--operation mode is normal

C1_num[2]_lut_out = C1L2 & (C1_num[2] $ (C1_num[1] & C1_num[0]));
C1_num[2] = DFFEAS(C1_num[2]_lut_out, B1_CLK_OUT, VCC, , C1L63, , , , );


--C1_num[1] is test_rec:inst1|num[1]
--operation mode is normal

C1_num[1]_lut_out = C1L2 & (C1_num[1] $ C1_num[0]);
C1_num[1] = DFFEAS(C1_num[1]_lut_out, B1_CLK_OUT, VCC, , C1L63, , , , );


--C1_num[0] is test_rec:inst1|num[0]
--operation mode is normal

C1_num[0]_lut_out = C1L2 & (!C1_num[0]);
C1_num[0] = DFFEAS(C1_num[0]_lut_out, B1_CLK_OUT, VCC, , C1L63, , , , );


--C1L14 is test_rec:inst1|reduce_nor~3
--operation mode is normal

C1L14 = C1_num[3] & C1_num[2] & C1_num[1] & C1_num[0];


--C1L22 is test_rec:inst1|data_out[7]~58
--operation mode is normal

C1L22 = C1_state[1] & (!C1_state[0]);


--C1L05 is test_rec:inst1|state~445
--operation mode is normal

C1L05 = !C1_state[0] & (C1_state[1] # rxd);


--C1_bit[2] is test_rec:inst1|bit[2]
--operation mode is normal

C1_bit[2]_lut_out = C1L21 & C1_bit[2] # !C1L21 & C1L8 & (C1_bit[2] $ C1L4);
C1_bit[2] = DFFEAS(C1_bit[2]_lut_out, B1_CLK_OUT, VCC, , , , , , );


--C1_bit[1] is test_rec:inst1|bit[1]
--operation mode is normal

C1_bit[1]_lut_out = C1L21 & C1_bit[1] # !C1L21 & C1L8 & (C1_bit[1] $ C1L5);
C1_bit[1] = DFFEAS(C1_bit[1]_lut_out, B1_CLK_OUT, VCC, , , , , , );


--C1_bit[0] is test_rec:inst1|bit[0]
--operation mode is normal

C1_bit[0]_lut_out = C1L21 & C1_bit[0] # !C1L21 & C1L8 & (C1_bit[0] $ C1L14);
C1_bit[0] = DFFEAS(C1_bit[0]_lut_out, B1_CLK_OUT, VCC, , , , , , );


--C1L11 is test_rec:inst1|bit[2]~583
--operation mode is normal

C1L11 = C1_bit[2] & C1_bit[1] & C1_bit[0];


--C1L74 is test_rec:inst1|state[0]~446
--operation mode is normal

C1L74 = C1_state[1] & C1L05 & (!C1L11 # !C1L14);


--C1_n[3] is test_rec:inst1|n[3]
--operation mode is arithmetic

C1_n[3]_carry_eqn = C1L03;
C1_n[3]_lut_out = C1_n[3] $ (C1_n[3]_carry_eqn);
C1_n[3] = DFFEAS(C1_n[3]_lut_out, B1_CLK_OUT, VCC, , C1L3, , , C1L05, );

--C1L23 is test_rec:inst1|n[3]~91
--operation mode is arithmetic

C1L23 = CARRY(!C1L03 # !C1_n[3]);


--C1_n[0] is test_rec:inst1|n[0]
--operation mode is arithmetic

C1_n[0]_lut_out = C1_n[0] $ C1L24;
C1_n[0] = DFFEAS(C1_n[0]_lut_out, B1_CLK_OUT, VCC, , C1L3, , , C1L05, );

--C1L62 is test_rec:inst1|n[0]~95
--operation mode is arithmetic

C1L62 = CARRY(C1_n[0] & C1L24);


--C1_n[1] is test_rec:inst1|n[1]
--operation mode is arithmetic

C1_n[1]_carry_eqn = C1L62;
C1_n[1]_lut_out = C1_n[1] $ (C1_n[1]_carry_eqn);
C1_n[1] = DFFEAS(C1_n[1]_lut_out, B1_CLK_OUT, VCC, , C1L3, , , C1L05, );

--C1L82 is test_rec:inst1|n[1]~99
--operation mode is arithmetic

C1L82 = CARRY(!C1L62 # !C1_n[1]);


--C1L34 is test_rec:inst1|reduce_nor~64
--operation mode is normal

C1L34 = !C1_n[1] # !C1_n[0];


--C1_n[4] is test_rec:inst1|n[4]
--operation mode is normal

C1_n[4]_carry_eqn = C1L23;
C1_n[4]_lut_out = C1_n[4] $ (!C1_n[4]_carry_eqn);
C1_n[4] = DFFEAS(C1_n[4]_lut_out, B1_CLK_OUT, VCC, , C1L3, , , C1L05, );


--C1_n[2] is test_rec:inst1|n[2]
--operation mode is arithmetic

C1_n[2]_carry_eqn = C1L82;
C1_n[2]_lut_out = C1_n[2] $ (!C1_n[2]_carry_eqn);
C1_n[2] = DFFEAS(C1_n[2]_lut_out, B1_CLK_OUT, VCC, , C1L3, , , C1L05, );

--C1L03 is test_rec:inst1|n[2]~107
--operation mode is arithmetic

C1L03 = CARRY(C1_n[2] & (!C1L82));


--C1L24 is test_rec:inst1|reduce_nor~4
--operation mode is normal

C1L24 = C1_n[3] # C1L34 # !C1_n[2] # !C1_n[4];


--C1L04 is test_rec:inst1|reduce_nor~1
--operation mode is normal

C1L04 = C1_num[2] & C1_num[1] & C1_num[0] & !C1_num[3];


--C1L84 is test_rec:inst1|state[0]~447
--operation mode is normal

C1L84 = !C1L05 & (C1_state[1] & C1L24 # !C1_state[1] & (!C1L04));


--E1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal

E1_hub_tdo = AMPP_FUNCTION(!A1L5, E1L31, E1L51, E1L71, E1L91, !KB1_state[8], KB1L81);


--B1_num[2] is did:inst|num[2]
--operation mode is normal

B1_num[2]_lut_out = B1L3 & (B1L12 # !B1_num[0] # !B1_num[1]);
B1_num[2] = DFFEAS(B1_num[2]_lut_out, CLK, VCC, , , , , , );


--B1_num[1] is did:inst|num[1]
--operation mode is normal

B1_num[1]_lut_out = B1L5;
B1_num[1] = DFFEAS(B1_num[1]_lut_out, CLK, VCC, , , , , , );


--B1L2 is did:inst|LessThan~83
--operation mode is normal

B1L2 = !B1_num[2] & !B1_num[1];


--B1_num[4] is did:inst|num[4]
--operation mode is normal

B1_num[4]_lut_out = B1L7 & (B1L12 # !B1_num[0] # !B1_num[1]);
B1_num[4] = DFFEAS(B1_num[4]_lut_out, CLK, VCC, , , , , , );


--B1_num[3] is did:inst|num[3]
--operation mode is normal

B1_num[3]_lut_out = B1L9;
B1_num[3] = DFFEAS(B1_num[3]_lut_out, CLK, VCC, , , , , , );


--B1_num[5] is did:inst|num[5]
--operation mode is normal

B1_num[5]_lut_out = B1L11 & (B1L12 # !B1_num[0] # !B1_num[1]);
B1_num[5] = DFFEAS(B1_num[5]_lut_out, CLK, VCC, , , , , , );


--C1L1 is test_rec:inst1|Select~548
--operation mode is normal

C1L1 = C1_state[1] # C1_state[0] # !rxd;


--C1L44 is test_rec:inst1|reduce_nor~65
--operation mode is normal

C1L44 = C1_num[2] & C1_num[1] & C1_num[0];


--C1L63 is test_rec:inst1|num[0]~86
--operation mode is normal

C1L63 = !C1_state[0] # !C1_state[1];


--C1L2 is test_rec:inst1|Select~550
--operation mode is normal

C1L2 = C1L1 & (C1L05 & (!C1L14) # !C1L05 & !C1L04);


--C1L21 is test_rec:inst1|bit[2]~584
--operation mode is normal

C1L21 = C1_state[1] & C1L11 & !C1L14 # !C1L05;


--C1L8 is test_rec:inst1|bit[0]~585
--operation mode is normal

C1L8 = C1_state[1] & (!C1_bit[0] # !C1_bit[1] # !C1_bit[2]);


--C1L4 is test_rec:inst1|add~313
--operation mode is normal

C1L4 = C1L14 & C1_bit[1] & C1_bit[0];


--C1L5 is test_rec:inst1|add~314
--operation mode is normal

C1L5 = C1L14 & C1_bit[0];


--C1L3 is test_rec:inst1|Select~554
--operation mode is normal

C1L3 = C1_state[1] & (C1_state[0]) # !C1_state[1] & rxd & !C1_state[0];


--HB4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

HB4_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !E1L2, E1L02);


--HB1_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
--operation mode is normal