rec.map.rpt

用verilog实现的串口收发数据程序

; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Maximum Number of M512 Memory Blocks                               ; -1           ; -1            ;
; Maximum Number of M4K Memory Blocks                                ; -1           ; -1            ;
; Maximum Number of M-RAM Memory Blocks                              ; -1           ; -1            ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; ../test_rec/test_rec.v           ; yes             ; User Verilog HDL File              ; F:/复件 FPGA程序/test_rec/test_rec.v                                   ;
; ../did/did.v                     ; yes             ; User Verilog HDL File              ; F:/复件 FPGA程序/did/did.v                                             ;
; rec.bdf                          ; yes             ; User Block Diagram/Schematic File  ; F:/复件 FPGA程序/rec/rec.bdf                                           ;
; sld_signaltap.vhd                ; yes             ; Encrypted Megafunction             ; d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd          ;
; sld_ela_control.vhd              ; yes             ; Encrypted Megafunction             ; d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd        ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf           ;
; lpm_constant.inc                 ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/lpm_constant.inc           ;
; dffeea.inc                       ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/dffeea.inc                 ;
; aglobal50.inc                    ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/aglobal50.inc              ;
; sld_mbpmg.vhd                    ; yes             ; Encrypted Megafunction             ; d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd              ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf            ;
; lpm_decode.inc                   ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/lpm_decode.inc             ;
; lpm_add_sub.inc                  ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.inc            ;
; cmpconst.inc                     ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/cmpconst.inc               ;
; lpm_compare.inc                  ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/lpm_compare.inc            ;
; lpm_counter.inc                  ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/lpm_counter.inc            ;
; alt_synch_counter.inc            ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc      ;
; alt_synch_counter_f.inc          ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc    ;
; alt_counter_f10ke.inc            ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc      ;
; alt_counter_stratix.inc          ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc    ;
; db/cntr_oo8.tdf                  ; yes             ; Auto-Generated Megafunction        ; F:/复件 FPGA程序/rec/db/cntr_oo8.tdf                                   ;
; db/cntr_g29.tdf                  ; yes             ; Auto-Generated Megafunction        ; F:/复件 FPGA程序/rec/db/cntr_g29.tdf                                   ;
; lpm_compare.tdf                  ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf            ;
; comptree.inc                     ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/comptree.inc               ;
; altshift.inc                     ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/altshift.inc               ;
; comptree.tdf                     ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/comptree.tdf               ;
; cmpchain.inc                     ; yes             ; Other                              ; d:/altera/quartus50/libraries/megafunctions/cmpchain.inc               ;
; cmpchain.tdf                     ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf               ;
; altshift.tdf                     ; yes             ; Megafunction                       ; d:/altera/quartus50/libraries/megafunctions/altshift.tdf               ;
; sld_acquisition_buffer.vhd       ; yes             ; Encrypted Megafunction             ; d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd ;