rec.map.summary

来自「用verilog实现的串口收发数据程序」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Fri Dec 14 23:12:17 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : rec
Top-level Entity Name : rec
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 445
Total pins : 18
Total virtual pins : 0
Total memory bits : 45,056
Total PLLs : 0