rec.tan.rpt

用verilog实现的串口收发数据程序

; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK                          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                 ; To                                                                                                                                                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 115.45 MHz ( period = 8.662 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 8.350 ns                ;
; N/A                                     ; 116.69 MHz ( period = 8.570 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                                                                                          ; CLK        ; CLK      ; None                        ; None                      ; 8.258 ns                ;
; N/A                                     ; 122.62 MHz ( period = 8.155 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 7.843 ns                ;
; N/A                                     ; 123.67 MHz ( period = 8.086 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 7.774 ns                ;
; N/A                                     ; 124.02 MHz ( period = 8.063 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                                                                                          ; CLK        ; CLK      ; None                        ; None                      ; 7.751 ns                ;
; N/A                                     ; 125.09 MHz ( period = 7.994 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|match_out  ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                                                                                          ; CLK        ; CLK      ; None                        ; None                      ; 7.682 ns                ;
; N/A                                     ; 125.63 MHz ( period = 7.960 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|match_out ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 7.648 ns                ;
; N/A                                     ; 126.89 MHz ( period = 7.881 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_g29:auto_generated|safe_q[7]                                           ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_g29:auto_generated|safe_q[3] ; CLK        ; CLK      ; None                        ; None                      ; 7.652 ns                ;
; N/A                                     ; 126.89 MHz ( period = 7.881 ns )                    ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_g29:auto_generated|safe_q[7]                                           ; sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_g29:auto_generated|safe_q[4] ; CLK        ; CLK      ; None                        ; None                      ; 7.652 ns                ;