test_rec.fit.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 3.30 1 12 0 " "Info: Number of I/O pins in group: 13 (unused VREF, 3.30 VCCIO, 1 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.176 ns register register " "Info: Estimated most critical path is register to register delay of 4.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\]~reg0 1 REG LAB_X14_Y11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y11; Fanout = 7; REG Node = 'state\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { state[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.114 ns) 1.368 ns state~536 2 COMB LAB_X16_Y11 11 " "Info: 2: + IC(1.254 ns) + CELL(0.114 ns) = 1.368 ns; Loc. = LAB_X16_Y11; Fanout = 11; COMB Node = 'state~536'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.368 ns" { state[0]~reg0 state~536 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.442 ns) 2.698 ns state\[1\]~537 3 COMB LAB_X14_Y11 2 " "Info: 3: + IC(0.888 ns) + CELL(0.442 ns) = 2.698 ns; Loc. = LAB_X14_Y11; Fanout = 2; COMB Node = 'state\[1\]~537'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.330 ns" { state~536 state[1]~537 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.478 ns) 4.176 ns state\[1\]~reg0 4 REG LAB_X16_Y11 12 " "Info: 4: + IC(1.000 ns) + CELL(0.478 ns) = 4.176 ns; Loc. = LAB_X16_Y11; Fanout = 12; REG Node = 'state\[1\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.478 ns" { state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.034 ns 24.76 % " "Info: Total cell delay = 1.034 ns ( 24.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.142 ns 75.24 % " "Info: Total interconnect delay = 3.142 ns ( 75.24 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.176 ns" { state[0]~reg0 state~536 state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: The following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "in_en VCC " "Info: Pin in_en has VCC driving its datain port" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 4 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "in_en" } } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { in_en } "NODE_NAME" } "" } } { "F:/test_rec/test_rec.fld" "" { Floorplan "F:/test_rec/test_rec.fld" "" "" { in_en } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "vcc VCC " "Info: Pin vcc has VCC driving its datain port" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vcc" } } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { vcc } "NODE_NAME" } "" } } { "F:/test_rec/test_rec.fld" "" { Floorplan "F:/test_rec/test_rec.fld" "" "" { vcc } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 12 21:32:12 2007 " "Info: Processing ended: Fri Oct 12 21:32:12 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}