test_rec.tan.rpt

用verilog实现的串口收发数据程序

+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; -5.090 ns ; rxd  ; data_out[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.234 ns ; rxd  ; num[3]           ; clk      ;
; N/A           ; None        ; -6.492 ns ; rxd  ; state[1]~reg0    ; clk      ;
; N/A           ; None        ; -7.148 ns ; rxd  ; n[3]             ; clk      ;
; N/A           ; None        ; -7.148 ns ; rxd  ; n[2]             ; clk      ;
; N/A           ; None        ; -7.148 ns ; rxd  ; n[1]             ; clk      ;
; N/A           ; None        ; -7.148 ns ; rxd  ; n[4]             ; clk      ;
; N/A           ; None        ; -7.148 ns ; rxd  ; n[0]             ; clk      ;
; N/A           ; None        ; -7.241 ns ; rxd  ; num[0]           ; clk      ;
; N/A           ; None        ; -7.245 ns ; rxd  ; num[1]           ; clk      ;
; N/A           ; None        ; -7.251 ns ; rxd  ; num[2]           ; clk      ;
; N/A           ; None        ; -7.289 ns ; rxd  ; state[0]~reg0    ; clk      ;
; N/A           ; None        ; -8.018 ns ; rxd  ; bit[2]           ; clk      ;
; N/A           ; None        ; -8.467 ns ; rxd  ; bit[0]           ; clk      ;
; N/A           ; None        ; -8.469 ns ; rxd  ; bit[1]           ; clk      ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 12 21:32:41 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test_rec -c test_rec --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 201.37 MHz between source register "state[0]~reg0" and destination register "state[1]~reg0" (period= 4.966 ns)
    Info: + Longest register to register delay is 4.705 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state[0]~reg0'
        Info: 2: + IC(1.260 ns) + CELL(0.114 ns) = 1.374 ns; Loc. = LC_X16_Y11_N4; Fanout = 11; COMB Node = 'state~536'
        Info: 3: + IC(1.240 ns) + CELL(0.590 ns) = 3.204 ns; Loc. = LC_X14_Y11_N8; Fanout = 2; COMB Node = 'state[1]~537'
        Info: 4: + IC(1.192 ns) + CELL(0.309 ns) = 4.705 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state[1]~reg0'
        Info: Total cell delay = 1.013 ns ( 21.53 % )
        Info: Total interconnect delay = 3.692 ns ( 78.47 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state[1]~reg0'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
        Info: - Longest clock path from clock "clk" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state[0]~reg0'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "state[1]~reg0" (data pin = "rxd", clock pin = "clk") is 8.936 ns
    Info: + Longest pin to register delay is 11.824 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_213; Fanout = 4; PIN Node = 'rxd'
        Info: 2: + IC(6.726 ns) + CELL(0.292 ns) = 8.493 ns; Loc. = LC_X16_Y11_N4; Fanout = 11; COMB Node = 'state~536'
        Info: 3: + IC(1.240 ns) + CELL(0.590 ns) = 10.323 ns; Loc. = LC_X14_Y11_N8; Fanout = 2; COMB Node = 'state[1]~537'
        Info: 4: + IC(1.192 ns) + CELL(0.309 ns) = 11.824 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state[1]~reg0'
        Info: Total cell delay = 2.666 ns ( 22.55 % )
        Info: Total interconnect delay = 9.158 ns ( 77.45 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state[1]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: tco from clock "clk" to destination pin "state[0]" through register "state[0]~reg0" is 7.887 ns
    Info: + Longest clock path from clock "clk" to source register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.738 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state[0]~reg0'
        Info: 2: + IC(2.630 ns) + CELL(2.108 ns) = 4.738 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'state[0]'
        Info: Total cell delay = 2.108 ns ( 44.49 % )
        Info: Total interconnect delay = 2.630 ns ( 55.51 % )
Info: th for register "data_out[0]~reg0" (data pin = "rxd", clock pin = "clk") is -5.090 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N9; Fanout = 2; REG Node = 'data_out[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.030 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_213; Fanout = 4; PIN Node = 'rxd'
        Info: 2: + IC(6.246 ns) + CELL(0.309 ns) = 8.030 ns; Loc. = LC_X13_Y11_N9; Fanout = 2; REG Node = 'data_out[0]~reg0'
        Info: Total cell delay = 1.784 ns ( 22.22 % )
        Info: Total interconnect delay = 6.246 ns ( 77.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 12 21:32:42 2007
    Info: Elapsed time: 00:00:02