test_rec.map.summary

用verilog实现的串口收发数据程序

Flow Status : Successful - Fri Oct 12 21:32:06 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : test_rec
Top-level Entity Name : test_rec
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 40
Total pins : 14
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0