test_rec.map.eqn

用verilog实现的串口收发数据程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L81Q is data_out[0]~reg0
--operation mode is normal

A1L81Q_lut_out = rxd;
A1L81Q = DFFEAS(A1L81Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L02Q is data_out[1]~reg0
--operation mode is normal

A1L02Q_lut_out = A1L81Q;
A1L02Q = DFFEAS(A1L02Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L22Q is data_out[2]~reg0
--operation mode is normal

A1L22Q_lut_out = A1L02Q;
A1L22Q = DFFEAS(A1L22Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L42Q is data_out[3]~reg0
--operation mode is normal

A1L42Q_lut_out = A1L22Q;
A1L42Q = DFFEAS(A1L42Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L62Q is data_out[4]~reg0
--operation mode is normal

A1L62Q_lut_out = A1L42Q;
A1L62Q = DFFEAS(A1L62Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L82Q is data_out[5]~reg0
--operation mode is normal

A1L82Q_lut_out = A1L62Q;
A1L82Q = DFFEAS(A1L82Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L03Q is data_out[6]~reg0
--operation mode is normal

A1L03Q_lut_out = A1L82Q;
A1L03Q = DFFEAS(A1L03Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L23Q is data_out[7]~reg0
--operation mode is normal

A1L23Q_lut_out = A1L03Q;
A1L23Q = DFFEAS(A1L23Q_lut_out, clk, VCC, , A1L61, , , , );


--A1L75Q is state[0]~reg0
--operation mode is normal

A1L75Q_lut_out = A1L06 & (!A1L26) # !A1L06 & (A1L71 # A1L95 & !A1L26);
A1L75Q = DFFEAS(A1L75Q_lut_out, clk, VCC, , , , , , );


--A1L16Q is state[1]~reg0
--operation mode is normal

A1L16Q_lut_out = A1L16Q $ (!A1L26 & !A1L06 & !A1L95);
A1L16Q = DFFEAS(A1L16Q_lut_out, clk, VCC, , , , , , );


--num[3] is num[3]
--operation mode is normal

num[3]_lut_out = A1L1 & (num[3] & (!A1L35) # !num[3] & A1L26 & A1L35);
num[3] = DFFEAS(num[3]_lut_out, clk, VCC, , A1L94, , , , );


--num[2] is num[2]
--operation mode is normal

num[2]_lut_out = A1L2 & (num[2] $ (num[1] & num[0]));
num[2] = DFFEAS(num[2]_lut_out, clk, VCC, , A1L94, , , , );


--num[1] is num[1]
--operation mode is normal

num[1]_lut_out = A1L2 & (num[1] $ num[0]);
num[1] = DFFEAS(num[1]_lut_out, clk, VCC, , A1L94, , , , );


--num[0] is num[0]
--operation mode is normal

num[0]_lut_out = A1L2 & (!num[0]);
num[0] = DFFEAS(num[0]_lut_out, clk, VCC, , A1L94, , , , );


--A1L05 is reduce_nor~3
--operation mode is normal

A1L05 = num[3] & num[2] & num[1] & num[0];


--A1L61 is data_out[0]~66
--operation mode is normal

A1L61 = A1L16Q & A1L05 & (!A1L75Q);


--A1L71 is data_out[0]~67
--operation mode is normal

A1L71 = A1L16Q & (!A1L75Q);


--n[3] is n[3]
--operation mode is arithmetic

n[3]_carry_eqn = A1L04;
n[3]_lut_out = n[3] $ (n[3]_carry_eqn);
n[3] = DFFEAS(n[3]_lut_out, clk, VCC, , A1L3, , , A1L26, );

--A1L24 is n[3]~91
--operation mode is arithmetic

A1L24 = CARRY(!A1L04 # !n[3]);


--n[0] is n[0]
--operation mode is arithmetic

n[0]_lut_out = n[0] $ A1L15;
n[0] = DFFEAS(n[0]_lut_out, clk, VCC, , A1L3, , , A1L26, );

--A1L63 is n[0]~95
--operation mode is arithmetic

A1L63 = CARRY(n[0] & A1L15);


--n[1] is n[1]
--operation mode is arithmetic

n[1]_carry_eqn = A1L63;
n[1]_lut_out = n[1] $ (n[1]_carry_eqn);
n[1] = DFFEAS(n[1]_lut_out, clk, VCC, , A1L3, , , A1L26, );

--A1L83 is n[1]~99
--operation mode is arithmetic

A1L83 = CARRY(!A1L63 # !n[1]);


--A1L25 is reduce_nor~63
--operation mode is normal

A1L25 = !n[1] # !n[0];


--n[4] is n[4]
--operation mode is normal

n[4]_carry_eqn = A1L24;
n[4]_lut_out = n[4] $ (!n[4]_carry_eqn);
n[4] = DFFEAS(n[4]_lut_out, clk, VCC, , A1L3, , , A1L26, );


--n[2] is n[2]
--operation mode is arithmetic

n[2]_carry_eqn = A1L83;
n[2]_lut_out = n[2] $ (!n[2]_carry_eqn);
n[2] = DFFEAS(n[2]_lut_out, clk, VCC, , A1L3, , , A1L26, );

--A1L04 is n[2]~107
--operation mode is arithmetic

A1L04 = CARRY(n[2] & (!A1L83));


--A1L15 is reduce_nor~4
--operation mode is normal

A1L15 = n[3] # A1L25 # !n[2] # !n[4];


--A1L35 is reduce_nor~64
--operation mode is normal

A1L35 = num[2] & num[1] & num[0];


--A1L95 is state[1]~535
--operation mode is normal

A1L95 = A1L16Q & A1L15 # !A1L16Q & (num[3] # !A1L35);


--A1L26 is state~536
--operation mode is normal

A1L26 = !A1L75Q & (A1L16Q # rxd);


--bit[2] is bit[2]
--operation mode is normal

bit[2]_lut_out = A1L21 & bit[2] # !A1L21 & A1L8 & (bit[2] $ A1L4);
bit[2] = DFFEAS(bit[2]_lut_out, clk, VCC, , , , , , );


--bit[1] is bit[1]
--operation mode is normal

bit[1]_lut_out = A1L21 & bit[1] # !A1L21 & A1L8 & (bit[1] $ A1L5);
bit[1] = DFFEAS(bit[1]_lut_out, clk, VCC, , , , , , );


--bit[0] is bit[0]
--operation mode is normal

bit[0]_lut_out = A1L21 & bit[0] # !A1L21 & A1L8 & (bit[0] $ A1L05);
bit[0] = DFFEAS(bit[0]_lut_out, clk, VCC, , , , , , );


--A1L11 is bit[2]~583
--operation mode is normal

A1L11 = bit[2] & bit[1] & bit[0];


--A1L06 is state[1]~537
--operation mode is normal

A1L06 = A1L16Q & A1L26 & (!A1L11 # !A1L05);


--A1L1 is Select~521
--operation mode is normal

A1L1 = A1L75Q # A1L16Q # !rxd;


--A1L94 is num[3]~86
--operation mode is normal

A1L94 = !A1L16Q # !A1L75Q;


--A1L2 is Select~523
--operation mode is normal

A1L2 = A1L1 & (num[3] $ A1L26 # !A1L35);


--A1L3 is Select~527
--operation mode is normal

A1L3 = A1L75Q & A1L16Q # !A1L75Q & !A1L16Q & rxd;


--A1L21 is bit[2]~584
--operation mode is normal

A1L21 = A1L16Q & A1L11 & !A1L05 # !A1L26;


--A1L8 is bit[0]~585
--operation mode is normal

A1L8 = A1L16Q & (!bit[0] # !bit[1] # !bit[2]);


--A1L4 is add~313
--operation mode is normal

A1L4 = A1L05 & bit[1] & bit[0];


--A1L5 is add~314
--operation mode is normal

A1L5 = A1L05 & bit[0];


--rxd is rxd
--operation mode is input

rxd = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--data_out[0] is data_out[0]
--operation mode is output

data_out[0] = OUTPUT(A1L81Q);


--data_out[1] is data_out[1]
--operation mode is output

data_out[1] = OUTPUT(A1L02Q);


--data_out[2] is data_out[2]
--operation mode is output

data_out[2] = OUTPUT(A1L22Q);


--data_out[3] is data_out[3]
--operation mode is output

data_out[3] = OUTPUT(A1L42Q);


--data_out[4] is data_out[4]
--operation mode is output

data_out[4] = OUTPUT(A1L62Q);


--data_out[5] is data_out[5]
--operation mode is output

data_out[5] = OUTPUT(A1L82Q);


--data_out[6] is data_out[6]
--operation mode is output

data_out[6] = OUTPUT(A1L03Q);


--data_out[7] is data_out[7]
--operation mode is output

data_out[7] = OUTPUT(A1L23Q);


--in_en is in_en
--operation mode is output

in_en = OUTPUT(VCC);


--vcc is vcc
--operation mode is output

vcc = OUTPUT(VCC);


--state[0] is state[0]
--operation mode is output

state[0] = OUTPUT(A1L75Q);


--state[1] is state[1]
--operation mode is output

state[1] = OUTPUT(A1L16Q);