📄 test_rec.fit.eqn
字号:
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L81Q is data_out[0]~reg0 at LC_X13_Y11_N9
--operation mode is normal
A1L81Q_lut_out = rxd;
A1L81Q = DFFEAS(A1L81Q_lut_out, GLOBAL(clk), VCC, , A1L61, , , , );
--A1L02Q is data_out[1]~reg0 at LC_X13_Y11_N1
--operation mode is normal
A1L02Q_lut_out = GND;
A1L02Q = DFFEAS(A1L02Q_lut_out, GLOBAL(clk), VCC, , A1L61, A1L81Q, , , VCC);
--A1L22Q is data_out[2]~reg0 at LC_X13_Y11_N8
--operation mode is normal
A1L22Q_lut_out = A1L02Q;
A1L22Q = DFFEAS(A1L22Q_lut_out, GLOBAL(clk), VCC, , A1L61, , , , );
--A1L42Q is data_out[3]~reg0 at LC_X13_Y11_N0
--operation mode is normal
A1L42Q_lut_out = GND;
A1L42Q = DFFEAS(A1L42Q_lut_out, GLOBAL(clk), VCC, , A1L61, A1L22Q, , , VCC);
--A1L62Q is data_out[4]~reg0 at LC_X13_Y11_N5
--operation mode is normal
A1L62Q_lut_out = A1L42Q;
A1L62Q = DFFEAS(A1L62Q_lut_out, GLOBAL(clk), VCC, , A1L61, , , , );
--A1L82Q is data_out[5]~reg0 at LC_X13_Y11_N4
--operation mode is normal
A1L82Q_lut_out = A1L62Q;
A1L82Q = DFFEAS(A1L82Q_lut_out, GLOBAL(clk), VCC, , A1L61, , , , );
--A1L03Q is data_out[6]~reg0 at LC_X13_Y11_N3
--operation mode is normal
A1L03Q_lut_out = GND;
A1L03Q = DFFEAS(A1L03Q_lut_out, GLOBAL(clk), VCC, , A1L61, A1L82Q, , , VCC);
--A1L23Q is data_out[7]~reg0 at LC_X13_Y11_N2
--operation mode is normal
A1L23Q_lut_out = A1L03Q;
A1L23Q = DFFEAS(A1L23Q_lut_out, GLOBAL(clk), VCC, , A1L61, , , , );
--A1L16Q is state[0]~reg0 at LC_X14_Y11_N9
--operation mode is normal
A1L16Q_lut_out = A1L46 & (!A1L66) # !A1L46 & (A1L71 # A1L36 & !A1L66);
A1L16Q = DFFEAS(A1L16Q_lut_out, GLOBAL(clk), VCC, , , , , , );
--A1L56Q is state[1]~reg0 at LC_X16_Y11_N1
--operation mode is normal
A1L56Q_lut_out = A1L56Q $ (!A1L36 & !A1L66 & !A1L46);
A1L56Q = DFFEAS(A1L56Q_lut_out, GLOBAL(clk), VCC, , , , , , );
--num[3] is num[3] at LC_X14_Y11_N5
--operation mode is normal
num[3]_lut_out = A1L1 & (num[3] & (!A1L75) # !num[3] & A1L66 & A1L75);
num[3] = DFFEAS(num[3]_lut_out, GLOBAL(clk), VCC, , A1L35, , , , );
--num[2] is num[2] at LC_X14_Y11_N0
--operation mode is normal
num[2]_lut_out = A1L2 & (num[2] $ (num[1] & num[0]));
num[2] = DFFEAS(num[2]_lut_out, GLOBAL(clk), VCC, , A1L35, , , , );
--num[1] is num[1] at LC_X14_Y11_N6
--operation mode is normal
num[1]_lut_out = A1L2 & (num[0] $ (num[1]));
num[1] = DFFEAS(num[1]_lut_out, GLOBAL(clk), VCC, , A1L35, , , , );
--num[0] is num[0] at LC_X14_Y11_N3
--operation mode is normal
num[0]_lut_out = A1L2 & (!num[0]);
num[0] = DFFEAS(num[0]_lut_out, GLOBAL(clk), VCC, , A1L35, , , , );
--A1L45 is reduce_nor~3 at LC_X14_Y11_N7
--operation mode is normal
A1L45 = num[1] & num[0] & num[3] & num[2];
--A1L61 is data_out[0]~66 at LC_X14_Y11_N2
--operation mode is normal
A1L61 = !A1L16Q & A1L56Q & A1L45;
--A1L71 is data_out[0]~67 at LC_X15_Y11_N9
--operation mode is normal
A1L71 = A1L56Q & (!A1L16Q);
--n[3] is n[3] at LC_X16_Y11_N8
--operation mode is arithmetic
n[3]_lut_out = n[3] $ A1L24;
n[3] = DFFEAS(n[3]_lut_out, GLOBAL(clk), VCC, , A1L3, , , A1L66, );
--A1L54 is n[3]~91 at LC_X16_Y11_N8
--operation mode is arithmetic
A1L54_cout_0 = !A1L24 # !n[3];
A1L54 = CARRY(A1L54_cout_0);
--A1L64 is n[3]~91COUT1_113 at LC_X16_Y11_N8
--operation mode is arithmetic
A1L64_cout_1 = !A1L34 # !n[3];
A1L64 = CARRY(A1L64_cout_1);
--n[0] is n[0] at LC_X16_Y11_N5
--operation mode is arithmetic
n[0]_lut_out = A1L55 $ n[0];
n[0] = DFFEAS(n[0]_lut_out, GLOBAL(clk), VCC, , A1L3, , , A1L66, );
--A1L63 is n[0]~95 at LC_X16_Y11_N5
--operation mode is arithmetic
A1L63_cout_0 = A1L55 & n[0];
A1L63 = CARRY(A1L63_cout_0);
--A1L73 is n[0]~95COUT1_111 at LC_X16_Y11_N5
--operation mode is arithmetic
A1L73_cout_1 = A1L55 & n[0];
A1L73 = CARRY(A1L73_cout_1);
--n[1] is n[1] at LC_X16_Y11_N6
--operation mode is arithmetic
n[1]_lut_out = n[1] $ (A1L63);
n[1] = DFFEAS(n[1]_lut_out, GLOBAL(clk), VCC, , A1L3, , , A1L66, );
--A1L93 is n[1]~99 at LC_X16_Y11_N6
--operation mode is arithmetic
A1L93_cout_0 = !A1L63 # !n[1];
A1L93 = CARRY(A1L93_cout_0);
--A1L04 is n[1]~99COUT1 at LC_X16_Y11_N6
--operation mode is arithmetic
A1L04_cout_1 = !A1L73 # !n[1];
A1L04 = CARRY(A1L04_cout_1);
--A1L65 is reduce_nor~63 at LC_X16_Y11_N0
--operation mode is normal
A1L65 = !n[1] # !n[0];
--n[4] is n[4] at LC_X16_Y11_N9
--operation mode is normal
n[4]_lut_out = n[4] $ (!A1L54);
n[4] = DFFEAS(n[4]_lut_out, GLOBAL(clk), VCC, , A1L3, , , A1L66, );
--n[2] is n[2] at LC_X16_Y11_N7
--operation mode is arithmetic
n[2]_lut_out = n[2] $ (!A1L93);
n[2] = DFFEAS(n[2]_lut_out, GLOBAL(clk), VCC, , A1L3, , , A1L66, );
--A1L24 is n[2]~107 at LC_X16_Y11_N7
--operation mode is arithmetic
A1L24_cout_0 = n[2] & (!A1L93);
A1L24 = CARRY(A1L24_cout_0);
--A1L34 is n[2]~107COUT1_112 at LC_X16_Y11_N7
--operation mode is arithmetic
A1L34_cout_1 = n[2] & (!A1L04);
A1L34 = CARRY(A1L34_cout_1);
--A1L55 is reduce_nor~4 at LC_X16_Y11_N2
--operation mode is normal
A1L55 = n[3] # A1L65 # !n[4] # !n[2];
--A1L75 is reduce_nor~64 at LC_X14_Y11_N4
--operation mode is normal
A1L75 = num[1] & num[2] & (num[0]);
--A1L36 is state[1]~535 at LC_X16_Y11_N3
--operation mode is normal
A1L36 = A1L56Q & (A1L55) # !A1L56Q & (num[3] # !A1L75);
--A1L66 is state~536 at LC_X16_Y11_N4
--operation mode is normal
A1L66 = !A1L16Q & (A1L56Q # rxd);
--bit[2] is bit[2] at LC_X15_Y11_N7
--operation mode is normal
bit[2]_lut_out = A1L21 & bit[2] # !A1L21 & A1L8 & (bit[2] $ A1L4);
bit[2] = DFFEAS(bit[2]_lut_out, GLOBAL(clk), VCC, , , , , , );
--bit[1] is bit[1] at LC_X15_Y11_N0
--operation mode is normal
bit[1]_lut_out = A1L21 & bit[1] # !A1L21 & A1L8 & (bit[1] $ A1L5);
bit[1] = DFFEAS(bit[1]_lut_out, GLOBAL(clk), VCC, , , , , , );
--bit[0] is bit[0] at LC_X15_Y11_N3
--operation mode is normal
bit[0]_lut_out = A1L21 & bit[0] # !A1L21 & A1L8 & (bit[0] $ A1L45);
bit[0] = DFFEAS(bit[0]_lut_out, GLOBAL(clk), VCC, , , , , , );
--A1L11 is bit[2]~583 at LC_X15_Y11_N5
--operation mode is normal
A1L11 = bit[1] & bit[2] & bit[0];
--A1L46 is state[1]~537 at LC_X14_Y11_N8
--operation mode is normal
A1L46 = A1L66 & A1L56Q & (!A1L45 # !A1L11);
--A1L1 is Select~521 at LC_X13_Y11_N7
--operation mode is normal
A1L1 = A1L56Q # A1L16Q # !rxd;
--A1L35 is num[3]~86 at LC_X15_Y11_N2
--operation mode is normal
A1L35 = !A1L16Q # !A1L56Q;
--A1L2 is Select~523 at LC_X14_Y11_N1
--operation mode is normal
A1L2 = A1L1 & (A1L66 $ num[3] # !A1L75);
--A1L3 is Select~527 at LC_X13_Y11_N6
--operation mode is normal
A1L3 = A1L56Q & (A1L16Q) # !A1L56Q & rxd & !A1L16Q;
--A1L21 is bit[2]~584 at LC_X15_Y11_N8
--operation mode is normal
A1L21 = A1L56Q & !A1L45 & A1L11 # !A1L66;
--A1L8 is bit[0]~585 at LC_X15_Y11_N4
--operation mode is normal
A1L8 = A1L56Q & (!bit[0] # !bit[2] # !bit[1]);
--A1L4 is add~313 at LC_X15_Y11_N6
--operation mode is normal
A1L4 = A1L45 & bit[1] & (bit[0]);
--A1L5 is add~314 at LC_X15_Y11_N1
--operation mode is normal
A1L5 = A1L45 & (bit[0]);
--rxd is rxd at PIN_213
--operation mode is input
rxd = INPUT();
--clk is clk at PIN_29
--operation mode is input
clk = INPUT();
--data_out[0] is data_out[0] at PIN_220
--operation mode is output
data_out[0] = OUTPUT(A1L81Q);
--data_out[1] is data_out[1] at PIN_219
--operation mode is output
data_out[1] = OUTPUT(A1L02Q);
--data_out[2] is data_out[2] at PIN_85
--operation mode is output
data_out[2] = OUTPUT(A1L22Q);
--data_out[3] is data_out[3] at PIN_84
--operation mode is output
data_out[3] = OUTPUT(A1L42Q);
--data_out[4] is data_out[4] at PIN_83
--operation mode is output
data_out[4] = OUTPUT(A1L62Q);
--data_out[5] is data_out[5] at PIN_218
--operation mode is output
data_out[5] = OUTPUT(A1L82Q);
--data_out[6] is data_out[6] at PIN_217
--operation mode is output
data_out[6] = OUTPUT(A1L03Q);
--data_out[7] is data_out[7] at PIN_80
--operation mode is output
data_out[7] = OUTPUT(A1L23Q);
--in_en is in_en at PIN_104
--operation mode is output
in_en = OUTPUT(VCC);
--vcc is vcc at PIN_95
--operation mode is output
vcc = OUTPUT(VCC);
--state[0] is state[0] at PIN_215
--operation mode is output
state[0] = OUTPUT(A1L16Q);
--state[1] is state[1] at PIN_86
--operation mode is output
state[1] = OUTPUT(A1L56Q);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -