vesa_vga_timesim.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

  signal NlwInverterSignal_DE_MC_D2_PT_14_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_8_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_5_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_5_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_4_MC_D1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_4_MC_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_655_MC_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_655_MC_D2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_655_MC_D2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_6_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_6_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_1_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_0_MC_D1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_0_MC_D1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_7_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_PCLK_Count_7_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_2_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_3_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_4_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_9_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_5_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_0_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_6_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_1_MC_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_7_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_HSync_Count_8_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_F_A_0_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_F_A_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_9_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_9_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_9_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_9_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_10_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_11_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_12_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_13_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_14_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_15_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0049_MC_D2_PT_16_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_n0020_MC_D1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_6_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_7_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_8_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_n0036_MC_D2_PT_9_IN5 : STD_