vesa_vga_timesim.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

  signal F_A_15_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_15_MC_D : STD_LOGIC; 
  signal F_A_15_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_15_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_15_MC_D1 : STD_LOGIC; 
  signal F_A_15_MC_D2 : STD_LOGIC; 
  signal F_A_15_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_15_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_14_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_14_MC_D : STD_LOGIC; 
  signal F_A_14_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_14_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_14_MC_D1 : STD_LOGIC; 
  signal F_A_14_MC_D2 : STD_LOGIC; 
  signal F_A_14_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_14_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_14_MC_D2_PT_2 : STD_LOGIC; 
  signal F_A_16_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_16_MC_D : STD_LOGIC; 
  signal F_A_16_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_16_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_16_MC_D1 : STD_LOGIC; 
  signal F_A_16_MC_D2 : STD_LOGIC; 
  signal F_A_16_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_16_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_16_MC_D2_PT_2 : STD_LOGIC; 
  signal F_A_18_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_18_MC_D : STD_LOGIC; 
  signal F_A_18_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_18_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_18_MC_D1 : STD_LOGIC; 
  signal F_A_18_MC_D2 : STD_LOGIC; 
  signal F_A_18_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_18_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_17_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_17_MC_D : STD_LOGIC; 
  signal F_A_17_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_17_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_17_MC_D1 : STD_LOGIC; 
  signal F_A_17_MC_D2 : STD_LOGIC; 
  signal F_A_17_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_17_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_19_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_19_MC_D : STD_LOGIC; 
  signal F_A_19_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_19_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_19_MC_D1 : STD_LOGIC; 
  signal F_A_19_MC_D2 : STD_LOGIC; 
  signal F_A_19_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_19_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_20_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_20_MC_D : STD_LOGIC; 
  signal F_A_20_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_20_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_20_MC_D1 : STD_LOGIC; 
  signal F_A_20_MC_D2 : STD_LOGIC; 
  signal F_A_20_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_20_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_21_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_21_MC_D : STD_LOGIC; 
  signal F_A_21_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_21_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_21_MC_D1 : STD_LOGIC; 
  signal F_A_21_MC_D2 : STD_LOGIC; 
  signal F_A_21_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_21_MC_D2_PT_1 : STD_LOGIC; 
  signal SF6843_MC_Q : STD_LOGIC; 
  signal SF6843_MC_D : STD_LOGIC; 
  signal SF6843_MC_D1 : STD_LOGIC; 
  signal SF6843_MC_D2 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_0 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_1 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_2 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_3 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_4 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_5 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_6 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_7 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_8 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_9 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_10 : STD_LOGIC; 
  signal SF6843_MC_D2_PT_11 : STD_LOGIC; 
  signal F_Byte_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_Byte_MC_D : STD_LOGIC; 
  signal F_Byte_MC_D1 : STD_LOGIC; 
  signal F_Byte_MC_D2 : STD_LOGIC; 
  signal F_E_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_E_1_MC_D : STD_LOGIC; 
  signal F_E_1_MC_D1 : STD_LOGIC; 
  signal F_E_1_MC_D2 : STD_LOGIC; 
  signal F_E_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_E_2_MC_D : STD_LOGIC; 
  signal F_E_2_MC_D1 : STD_LOGIC; 
  signal F_E_2_MC_D2 : STD_LOGIC; 
  signal F_E_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_E_3_MC_D : STD_LOGIC; 
  signal F_E_3_MC_D1 : STD_LOGIC; 
  signal F_E_3_MC_D2 : STD_LOGIC; 
  signal F_G_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_G_MC_D : STD_LOGIC; 
  signal F_G_MC_D1 : STD_LOGIC; 
  signal F_G_MC_D2 : STD_LOGIC; 
  signal F_RP_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_RP_MC_D : STD_LOGIC; 
  signal F_RP_MC_D1 : STD_LOGIC; 
  signal F_RP_MC_D2 : STD_LOGIC; 
  signal F_W_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_W_MC_D : STD_LOGIC; 
  signal F_W_MC_D1 : STD_LOGIC; 
  signal F_W_MC_D2 : STD_LOGIC; 
  signal G0_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_0_MC_D : STD_LOGIC; 
  signal G0_0_MC_D1 : STD_LOGIC; 
  signal G0_0_MC_D2 : STD_LOGIC; 
  signal G0_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_1_MC_D : STD_LOGIC; 
  signal G0_1_MC_D1 : STD_LOGIC; 
  signal G0_1_MC_D2 : STD_LOGIC; 
  signal G0_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_2_MC_D : STD_LOGIC; 
  signal G0_2_MC_D1 : STD_LOGIC; 
  signal G0_2_MC_D2 : STD_LOGIC; 
  signal G0_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_3_MC_D : STD_LOGIC; 
  signal G0_3_MC_D1 : STD_LOGIC; 
  signal G0_3_MC_D2 : STD_LOGIC; 
  signal G0_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_4_MC_D : STD_LOGIC; 
  signal G0_4_MC_D1 : STD_LOGIC; 
  signal G0_4_MC_D2 : STD_LOGIC; 
  signal G0_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_5_MC_D : STD_LOGIC; 
  signal G0_5_MC_D1 : STD_LOGIC; 
  signal G0_5_MC_D2 : STD_LOGIC; 
  signal G0_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_6_MC_D : STD_LOGIC; 
  signal G0_6_MC_D1 : STD_LOGIC; 
  signal G0_6_MC_D2 : STD_LOGIC; 
  signal G0_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G0_7_MC_D : STD_LOGIC; 
  signal G0_7_MC_D1 : STD_LOGIC; 
  signal G0_7_MC_D2 : STD_LOGIC; 
  signal G1_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_0_MC_D : STD_LOGIC; 
  signal G1_0_MC_D1 : STD_LOGIC; 
  signal G1_0_MC_D2 : STD_LOGIC; 
  signal G1_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_1_MC_D : STD_LOGIC; 
  signal G1_1_MC_D1 : STD_LOGIC; 
  signal G1_1_MC_D2 : STD_LOGIC; 
  signal G1_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_2_MC_D : STD_LOGIC; 
  signal G1_2_MC_D1 : STD_LOGIC; 
  signal G1_2_MC_D2 : STD_LOGIC; 
  signal G1_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_3_MC_D : STD_LOGIC; 
  signal G1_3_MC_D1 : STD_LOGIC; 
  signal G1_3_MC_D2 : STD_LOGIC; 
  signal G1_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_4_MC_D : STD_LOGIC; 
  signal G1_4_MC_D1 : STD_LOGIC; 
  signal G1_4_MC_D2 : STD_LOGIC; 
  signal G1_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_5_MC_D : STD_LOGIC; 
  signal G1_5_MC_D1 : STD_LOGIC; 
  signal G1_5_MC_D2 : STD_LOGIC; 
  signal G1_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_6_MC_D : STD_LOGIC; 
  signal G1_6_MC_D1 : STD_LOGIC; 
  signal G1_6_MC_D2 : STD_LOGIC; 
  signal G1_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal G1_7_MC_D : STD_LOGIC; 
  signal G1_7_MC_D1 : STD_LOGIC; 
  signal G1_7_MC_D2 : STD_LOGIC; 
  signal R0_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_0_MC_D : STD_LOGIC; 
  signal R0_0_MC_D1 : STD_LOGIC; 
  signal R0_0_MC_D2 : STD_LOGIC; 
  signal R0_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_1_MC_D : STD_LOGIC; 
  signal R0_1_MC_D1 : STD_LOGIC; 
  signal R0_1_MC_D2 : STD_LOGIC; 
  signal R0_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_2_MC_D : STD_LOGIC; 
  signal R0_2_MC_D1 : STD_LOGIC; 
  signal R0_2_MC_D2 : STD_LOGIC; 
  signal R0_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_3_MC_D : STD_LOGIC; 
  signal R0_3_MC_D1 : STD_LOGIC; 
  signal R0_3_MC_D2 : STD_LOGIC; 
  signal R0_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_4_MC_D : STD_LOGIC; 
  signal R0_4_MC_D1 : STD_LOGIC; 
  signal R0_4_MC_D2 : STD_LOGIC; 
  signal R0_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_5_MC_D : STD_LOGIC; 
  signal R0_5_MC_D1 : STD_LOGIC; 
  signal R0_5_MC_D2 : STD_LOGIC; 
  signal R0_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_6_MC_D : STD_LOGIC; 
  signal R0_6_MC_D1 : STD_LOGIC; 
  signal R0_6_MC_D2 : STD_LOGIC; 
  signal R0_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R0_7_MC_D : STD_LOGIC; 
  signal R0_7_MC_D1 : STD_LOGIC; 
  signal R0_7_MC_D2 : STD_LOGIC; 
  signal R1_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_0_MC_D : STD_LOGIC; 
  signal R1_0_MC_D1 : STD_LOGIC; 
  signal R1_0_MC_D2 : STD_LOGIC; 
  signal R1_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_1_MC_D : STD_LOGIC; 
  signal R1_1_MC_D1 : STD_LOGIC; 
  signal R1_1_MC_D2 : STD_LOGIC; 
  signal R1_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_2_MC_D : STD_LOGIC; 
  signal R1_2_MC_D1 : STD_LOGIC; 
  signal R1_2_MC_D2 : STD_LOGIC; 
  signal R1_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_3_MC_D : STD_LOGIC; 
  signal R1_3_MC_D1 : STD_LOGIC; 
  signal R1_3_MC_D2 : STD_LOGIC; 
  signal R1_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_4_MC_D : STD_LOGIC; 
  signal R1_4_MC_D1 : STD_LOGIC; 
  signal R1_4_MC_D2 : STD_LOGIC; 
  signal R1_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_5_MC_D : STD_LOGIC; 
  signal R1_5_MC_D1 : STD_LOGIC; 
  signal R1_5_MC_D2 : STD_LOGIC; 
  signal R1_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_6_MC_D : STD_LOGIC; 
  signal R1_6_MC_D1 : STD_LOGIC; 
  signal R1_6_MC_D2 : STD_LOGIC; 
  signal R1_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal R1_7_MC_D : STD_LOGIC; 
  signal R1_7_MC_D1 : STD_LOGIC; 
  signal R1_7_MC_D2 : STD_LOGIC; 
  signal VSync_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal VSync_MC_D : STD_LOGIC; 
  signal VSync_MC_D1 : STD_LOGIC; 
  signal VSync_MC_D2 : STD_LOGIC; 
  signal NlwInverterSignal_ODCK1X_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SET_Deb_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SET_Deb_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_SET_Deb_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_SET_Deb_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_SET_D0_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UP_Deb_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UP_Deb_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_UP_Deb_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_UP_Deb_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_UP_D0_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_10_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_10_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_10_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_11_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_11_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_11_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_11_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_11_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_12_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_12_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_12_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_12_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_12_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_13_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DE_MC_D2_PT_14_IN6 : STD_LOGIC;