vesa_vga_timesim.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

  signal HSync_Count_4_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_9_MC_Q : STD_LOGIC; 
  signal HSync_Count_9_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_9_MC_D : STD_LOGIC; 
  signal HSync_Count_9_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_9_MC_D1 : STD_LOGIC; 
  signal HSync_Count_9_MC_D2 : STD_LOGIC; 
  signal HSync_Count_9_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_9_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_9_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_5_MC_Q : STD_LOGIC; 
  signal HSync_Count_5_MC_D : STD_LOGIC; 
  signal HSync_Count_5_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_5_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_5_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_5_MC_D1 : STD_LOGIC; 
  signal HSync_Count_5_MC_D2 : STD_LOGIC; 
  signal HSync_Count_5_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_5_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_0_MC_Q : STD_LOGIC; 
  signal HSync_Count_0_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_0_MC_D : STD_LOGIC; 
  signal HSync_Count_0_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_0_MC_D1 : STD_LOGIC; 
  signal HSync_Count_0_MC_D2 : STD_LOGIC; 
  signal HSync_Count_0_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_0_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_0_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_6_MC_Q : STD_LOGIC; 
  signal HSync_Count_6_MC_D : STD_LOGIC; 
  signal HSync_Count_6_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_6_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_6_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_6_MC_D1 : STD_LOGIC; 
  signal HSync_Count_6_MC_D2 : STD_LOGIC; 
  signal HSync_Count_6_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_6_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_1_MC_Q : STD_LOGIC; 
  signal HSync_Count_1_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_1_MC_D : STD_LOGIC; 
  signal HSync_Count_1_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_1_MC_D1 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_3 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_4 : STD_LOGIC; 
  signal HSync_Count_1_MC_D2_PT_5 : STD_LOGIC; 
  signal HSync_Count_7_MC_Q : STD_LOGIC; 
  signal HSync_Count_7_MC_D : STD_LOGIC; 
  signal HSync_Count_7_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_7_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_7_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_7_MC_D1 : STD_LOGIC; 
  signal HSync_Count_7_MC_D2 : STD_LOGIC; 
  signal HSync_Count_7_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_7_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal HSync_MC_UIM : STD_LOGIC; 
  signal HSync_MC_D : STD_LOGIC; 
  signal HSync_MC_D1 : STD_LOGIC; 
  signal HSync_MC_D2 : STD_LOGIC; 
  signal HSync_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_8_MC_Q : STD_LOGIC; 
  signal HSync_Count_8_MC_D : STD_LOGIC; 
  signal HSync_Count_8_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_8_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_8_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_8_MC_D1 : STD_LOGIC; 
  signal HSync_Count_8_MC_D2 : STD_LOGIC; 
  signal HSync_Count_8_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_8_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_0_MC_UIM : STD_LOGIC; 
  signal F_A_0_MC_D : STD_LOGIC; 
  signal F_A_0_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_0_MC_D1 : STD_LOGIC; 
  signal F_A_0_MC_D2 : STD_LOGIC; 
  signal Q_n0049 : STD_LOGIC; 
  signal F_A_0_MC_D2_PT_0 : STD_LOGIC; 
  signal Q_n0036 : STD_LOGIC; 
  signal F_A_0_MC_D2_PT_1 : STD_LOGIC; 
  signal Q_n0049_MC_Q : STD_LOGIC; 
  signal Q_n0049_MC_D : STD_LOGIC; 
  signal Q_n0049_MC_D1 : STD_LOGIC; 
  signal Q_n0049_MC_D2 : STD_LOGIC; 
  signal Q_n0020 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_0 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_1 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_2 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_3 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_4 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_5 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_6 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_7 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_8 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_9 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_10 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_11 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_12 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_13 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_14 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_15 : STD_LOGIC; 
  signal Q_n0049_MC_D2_PT_16 : STD_LOGIC; 
  signal Q_n0020_MC_Q : STD_LOGIC; 
  signal Q_n0020_MC_D : STD_LOGIC; 
  signal Q_n0020_MC_D1 : STD_LOGIC; 
  signal Q_n0020_MC_D2 : STD_LOGIC; 
  signal Q_n0036_MC_Q : STD_LOGIC; 
  signal Q_n0036_MC_D : STD_LOGIC; 
  signal Q_n0036_MC_D1 : STD_LOGIC; 
  signal Q_n0036_MC_D2 : STD_LOGIC; 
  signal F_A_18_MC_UIM : STD_LOGIC; 
  signal F_A_17_MC_UIM : STD_LOGIC; 
  signal F_A_19_MC_UIM : STD_LOGIC; 
  signal F_A_20_MC_UIM : STD_LOGIC; 
  signal F_A_21_MC_UIM : STD_LOGIC; 
  signal SF6843 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_0 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_1 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_2 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_3 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_4 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_5 : STD_LOGIC; 
  signal F_A_16_MC_UIM : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_6 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_7 : STD_LOGIC; 
  signal F_A_13_MC_UIM : STD_LOGIC; 
  signal F_A_15_MC_UIM : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_8 : STD_LOGIC; 
  signal F_A_14_MC_UIM : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_9 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_10 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_11 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_12 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_13 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_14 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_15 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_16 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_17 : STD_LOGIC; 
  signal F_A_12_MC_UIM : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_18 : STD_LOGIC; 
  signal Q_n0036_MC_D2_PT_19 : STD_LOGIC; 
  signal F_A_13_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_13_MC_D : STD_LOGIC; 
  signal F_A_13_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_13_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_13_MC_D1 : STD_LOGIC; 
  signal F_A_13_MC_D2 : STD_LOGIC; 
  signal F_A_13_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_13_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_1_MC_UIM : STD_LOGIC; 
  signal F_A_2_MC_UIM : STD_LOGIC; 
  signal F_A_3_MC_UIM : STD_LOGIC; 
  signal F_A_4_MC_UIM : STD_LOGIC; 
  signal F_A_5_MC_UIM : STD_LOGIC; 
  signal F_A_6_MC_UIM : STD_LOGIC; 
  signal F_A_7_MC_UIM : STD_LOGIC; 
  signal F_A_8_MC_UIM : STD_LOGIC; 
  signal F_A_9_MC_UIM : STD_LOGIC; 
  signal F_A_10_MC_UIM : STD_LOGIC; 
  signal F_A_11_MC_UIM : STD_LOGIC; 
  signal F_A_13_MC_D2_PT_2 : STD_LOGIC; 
  signal F_A_10_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_10_MC_D : STD_LOGIC; 
  signal F_A_10_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_10_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_10_MC_D1 : STD_LOGIC; 
  signal F_A_10_MC_D2 : STD_LOGIC; 
  signal F_A_10_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_10_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_6_MC_D : STD_LOGIC; 
  signal F_A_6_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_6_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_6_MC_D1 : STD_LOGIC; 
  signal F_A_6_MC_D2 : STD_LOGIC; 
  signal F_A_6_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_6_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_1_MC_D : STD_LOGIC; 
  signal F_A_1_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_1_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_1_MC_D1 : STD_LOGIC; 
  signal F_A_1_MC_D2 : STD_LOGIC; 
  signal F_A_1_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_1_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_2_MC_D : STD_LOGIC; 
  signal F_A_2_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_2_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_2_MC_D1 : STD_LOGIC; 
  signal F_A_2_MC_D2 : STD_LOGIC; 
  signal F_A_2_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_2_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_3_MC_D : STD_LOGIC; 
  signal F_A_3_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_3_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_3_MC_D1 : STD_LOGIC; 
  signal F_A_3_MC_D2 : STD_LOGIC; 
  signal F_A_3_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_3_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_4_MC_D : STD_LOGIC; 
  signal F_A_4_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_4_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_4_MC_D1 : STD_LOGIC; 
  signal F_A_4_MC_D2 : STD_LOGIC; 
  signal F_A_4_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_4_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_5_MC_D : STD_LOGIC; 
  signal F_A_5_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_5_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_5_MC_D1 : STD_LOGIC; 
  signal F_A_5_MC_D2 : STD_LOGIC; 
  signal F_A_5_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_5_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_7_MC_D : STD_LOGIC; 
  signal F_A_7_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_7_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_7_MC_D1 : STD_LOGIC; 
  signal F_A_7_MC_D2 : STD_LOGIC; 
  signal F_A_7_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_7_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_8_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_8_MC_D : STD_LOGIC; 
  signal F_A_8_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_8_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_8_MC_D1 : STD_LOGIC; 
  signal F_A_8_MC_D2 : STD_LOGIC; 
  signal F_A_8_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_8_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_9_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_9_MC_D : STD_LOGIC; 
  signal F_A_9_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_9_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_9_MC_D1 : STD_LOGIC; 
  signal F_A_9_MC_D2 : STD_LOGIC; 
  signal F_A_9_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_9_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_12_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_12_MC_D : STD_LOGIC; 
  signal F_A_12_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_12_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_12_MC_D1 : STD_LOGIC; 
  signal F_A_12_MC_D2 : STD_LOGIC; 
  signal F_A_12_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_12_MC_D2_PT_1 : STD_LOGIC; 
  signal F_A_12_MC_D2_PT_2 : STD_LOGIC; 
  signal F_A_11_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal F_A_11_MC_D : STD_LOGIC; 
  signal F_A_11_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal F_A_11_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal F_A_11_MC_D1 : STD_LOGIC; 
  signal F_A_11_MC_D2 : STD_LOGIC; 
  signal F_A_11_MC_D2_PT_0 : STD_LOGIC; 
  signal F_A_11_MC_D2_PT_1 : STD_LOGIC; 
  signal Pages_2_MC_Q : STD_LOGIC; 
  signal FOOBAR5_ctinst_0 : STD_LOGIC; 
  signal Pages_2_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal Pages_2_MC_D : STD_LOGIC; 
  signal FOOBAR5_ctinst_5 : STD_LOGIC; 
  signal Pages_2_MC_D1 : STD_LOGIC; 
  signal Pages_2_MC_D2 : STD_LOGIC; 
  signal Pages_0_MC_Q : STD_LOGIC; 
  signal Pages_0_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal Pages_0_MC_D : STD_LOGIC; 
  signal Pages_0_MC_D1 : STD_LOGIC; 
  signal Pages_0_MC_D2 : STD_LOGIC; 
  signal Pages_1_MC_Q : STD_LOGIC; 
  signal Pages_1_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal Pages_1_MC_D : STD_LOGIC; 
  signal Pages_1_MC_D1 : STD_LOGIC; 
  signal Pages_1_MC_D2 : STD_LOGIC; 
  signal Pages_1_MC_D2_PT_0 : STD_LOGIC; 
  signal Pages_1_MC_D2_PT_1 : STD_LOGIC;