vesa_vga_timesim.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

  signal CLK_Deb_9_MC_D : STD_LOGIC; 
  signal CLK_Deb_9_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_9_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_9_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_11_MC_Q : STD_LOGIC; 
  signal CLK_Deb_11_MC_D : STD_LOGIC; 
  signal CLK_Deb_11_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_11_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_11_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_12_MC_Q : STD_LOGIC; 
  signal CLK_Deb_12_MC_D : STD_LOGIC; 
  signal CLK_Deb_12_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_12_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_12_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_13_MC_Q : STD_LOGIC; 
  signal CLK_Deb_13_MC_D : STD_LOGIC; 
  signal CLK_Deb_13_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_13_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_13_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_14_MC_Q : STD_LOGIC; 
  signal CLK_Deb_14_MC_D : STD_LOGIC; 
  signal CLK_Deb_14_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_14_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_14_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_15_MC_Q : STD_LOGIC; 
  signal CLK_Deb_15_MC_D : STD_LOGIC; 
  signal CLK_Deb_15_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_15_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_15_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_16_MC_Q : STD_LOGIC; 
  signal CLK_Deb_16_MC_D : STD_LOGIC; 
  signal CLK_Deb_16_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_16_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_16_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_17_MC_Q : STD_LOGIC; 
  signal CLK_Deb_17_MC_D : STD_LOGIC; 
  signal CLK_Deb_17_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_17_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_17_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_18_MC_Q : STD_LOGIC; 
  signal CLK_Deb_18_MC_D : STD_LOGIC; 
  signal CLK_Deb_18_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_18_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_18_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_19_MC_Q : STD_LOGIC; 
  signal CLK_Deb_19_MC_D : STD_LOGIC; 
  signal CLK_Deb_19_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_19_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_19_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_20_MC_Q : STD_LOGIC; 
  signal CLK_Deb_20_MC_D : STD_LOGIC; 
  signal CLK_Deb_20_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_20_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_20_MC_D2 : STD_LOGIC; 
  signal SET_D1_MC_Q : STD_LOGIC; 
  signal SET_D1_MC_D : STD_LOGIC; 
  signal SET_D1_MC_D1 : STD_LOGIC; 
  signal SET_D1_MC_D2 : STD_LOGIC; 
  signal UP_Deb_MC_Q : STD_LOGIC; 
  signal UP_Deb : STD_LOGIC; 
  signal UP_Deb_MC_D : STD_LOGIC; 
  signal UP_Deb_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal UP_Deb_MC_D1 : STD_LOGIC; 
  signal UP_Deb_MC_D2 : STD_LOGIC; 
  signal UP_D1 : STD_LOGIC; 
  signal UP_Deb_MC_D2_PT_0 : STD_LOGIC; 
  signal UP_D0 : STD_LOGIC; 
  signal UP_Deb_MC_D2_PT_1 : STD_LOGIC; 
  signal UP_D0_MC_Q : STD_LOGIC; 
  signal UP_D0_MC_D : STD_LOGIC; 
  signal FOOBAR5_ctinst_4 : STD_LOGIC; 
  signal UP_D0_MC_D1 : STD_LOGIC; 
  signal UP_D0_MC_D2 : STD_LOGIC; 
  signal UP_D1_MC_Q : STD_LOGIC; 
  signal UP_D1_MC_D : STD_LOGIC; 
  signal UP_D1_MC_D1 : STD_LOGIC; 
  signal UP_D1_MC_D2 : STD_LOGIC; 
  signal B0_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_1_MC_D : STD_LOGIC; 
  signal B0_1_MC_D1 : STD_LOGIC; 
  signal B0_1_MC_D2 : STD_LOGIC; 
  signal B0_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_2_MC_D : STD_LOGIC; 
  signal B0_2_MC_D1 : STD_LOGIC; 
  signal B0_2_MC_D2 : STD_LOGIC; 
  signal B0_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_3_MC_D : STD_LOGIC; 
  signal B0_3_MC_D1 : STD_LOGIC; 
  signal B0_3_MC_D2 : STD_LOGIC; 
  signal B0_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_4_MC_D : STD_LOGIC; 
  signal B0_4_MC_D1 : STD_LOGIC; 
  signal B0_4_MC_D2 : STD_LOGIC; 
  signal B0_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_5_MC_D : STD_LOGIC; 
  signal B0_5_MC_D1 : STD_LOGIC; 
  signal B0_5_MC_D2 : STD_LOGIC; 
  signal B0_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_6_MC_D : STD_LOGIC; 
  signal B0_6_MC_D1 : STD_LOGIC; 
  signal B0_6_MC_D2 : STD_LOGIC; 
  signal B0_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_7_MC_D : STD_LOGIC; 
  signal B0_7_MC_D1 : STD_LOGIC; 
  signal B0_7_MC_D2 : STD_LOGIC; 
  signal B1_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_0_MC_D : STD_LOGIC; 
  signal B1_0_MC_D1 : STD_LOGIC; 
  signal B1_0_MC_D2 : STD_LOGIC; 
  signal B1_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_1_MC_D : STD_LOGIC; 
  signal B1_1_MC_D1 : STD_LOGIC; 
  signal B1_1_MC_D2 : STD_LOGIC; 
  signal B1_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_2_MC_D : STD_LOGIC; 
  signal B1_2_MC_D1 : STD_LOGIC; 
  signal B1_2_MC_D2 : STD_LOGIC; 
  signal B1_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_3_MC_D : STD_LOGIC; 
  signal B1_3_MC_D1 : STD_LOGIC; 
  signal B1_3_MC_D2 : STD_LOGIC; 
  signal B1_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_4_MC_D : STD_LOGIC; 
  signal B1_4_MC_D1 : STD_LOGIC; 
  signal B1_4_MC_D2 : STD_LOGIC; 
  signal B1_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_5_MC_D : STD_LOGIC; 
  signal B1_5_MC_D1 : STD_LOGIC; 
  signal B1_5_MC_D2 : STD_LOGIC; 
  signal B1_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_6_MC_D : STD_LOGIC; 
  signal B1_6_MC_D1 : STD_LOGIC; 
  signal B1_6_MC_D2 : STD_LOGIC; 
  signal B1_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B1_7_MC_D : STD_LOGIC; 
  signal B1_7_MC_D1 : STD_LOGIC; 
  signal B1_7_MC_D2 : STD_LOGIC; 
  signal DE_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal DE_MC_D : STD_LOGIC; 
  signal DE_MC_D1 : STD_LOGIC; 
  signal DE_MC_D2 : STD_LOGIC; 
  signal N_PZ_655 : STD_LOGIC; 
  signal DE_MC_D2_PT_0 : STD_LOGIC; 
  signal DE_MC_D2_PT_1 : STD_LOGIC; 
  signal DE_MC_D2_PT_2 : STD_LOGIC; 
  signal DE_MC_D2_PT_3 : STD_LOGIC; 
  signal DE_MC_D2_PT_4 : STD_LOGIC; 
  signal DE_MC_D2_PT_5 : STD_LOGIC; 
  signal DE_MC_D2_PT_6 : STD_LOGIC; 
  signal DE_MC_D2_PT_7 : STD_LOGIC; 
  signal DE_MC_D2_PT_8 : STD_LOGIC; 
  signal DE_MC_D2_PT_9 : STD_LOGIC; 
  signal DE_MC_D2_PT_10 : STD_LOGIC; 
  signal DE_MC_D2_PT_11 : STD_LOGIC; 
  signal DE_MC_D2_PT_12 : STD_LOGIC; 
  signal DE_MC_D2_PT_13 : STD_LOGIC; 
  signal DE_MC_D2_PT_14 : STD_LOGIC; 
  signal PCLK_Count_8_MC_Q : STD_LOGIC; 
  signal PCLK_Count_8_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_8_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_8_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_8_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_8_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_8_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_8_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_8_MC_D2_PT_2 : STD_LOGIC; 
  signal PCLK_Count_9_MC_Q : STD_LOGIC; 
  signal PCLK_Count_9_MC_D : STD_LOGIC; 
  signal PCLK_Count_9_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal PCLK_Count_9_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_9_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_9_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_9_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_9_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_9_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_9_MC_D2_PT_2 : STD_LOGIC; 
  signal PCLK_Count_5_MC_Q : STD_LOGIC; 
  signal PCLK_Count_5_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_5_MC_D : STD_LOGIC; 
  signal PCLK_Count_5_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_5_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_5_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_5_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_5_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_5_MC_D2_PT_2 : STD_LOGIC; 
  signal PCLK_Count_4_MC_Q : STD_LOGIC; 
  signal PCLK_Count_4_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_4_MC_D : STD_LOGIC; 
  signal PCLK_Count_4_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_4_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_4_MC_D2 : STD_LOGIC; 
  signal N_PZ_655_MC_Q : STD_LOGIC; 
  signal N_PZ_655_MC_D : STD_LOGIC; 
  signal N_PZ_655_MC_D1 : STD_LOGIC; 
  signal N_PZ_655_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_6_MC_Q : STD_LOGIC; 
  signal PCLK_Count_6_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_6_MC_D : STD_LOGIC; 
  signal PCLK_Count_6_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_6_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_6_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_6_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_6_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_6_MC_D2_PT_2 : STD_LOGIC; 
  signal PCLK_Count_1_MC_Q : STD_LOGIC; 
  signal PCLK_Count_1_MC_D : STD_LOGIC; 
  signal PCLK_Count_1_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal PCLK_Count_1_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_1_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_1_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_1_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_1_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_1_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_0_MC_Q : STD_LOGIC; 
  signal PCLK_Count_0_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_0_MC_D : STD_LOGIC; 
  signal PCLK_Count_0_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_0_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_0_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_2_MC_Q : STD_LOGIC; 
  signal PCLK_Count_2_MC_D : STD_LOGIC; 
  signal PCLK_Count_2_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal PCLK_Count_2_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_2_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_2_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_2_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_2_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_2_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_3_MC_Q : STD_LOGIC; 
  signal PCLK_Count_3_MC_D : STD_LOGIC; 
  signal PCLK_Count_3_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal PCLK_Count_3_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_3_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_3_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_3_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_3_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_3_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_7_MC_Q : STD_LOGIC; 
  signal PCLK_Count_7_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal PCLK_Count_7_MC_D : STD_LOGIC; 
  signal PCLK_Count_7_MC_REG_tsimcreated_inv_FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal PCLK_Count_7_MC_D1 : STD_LOGIC; 
  signal PCLK_Count_7_MC_D2 : STD_LOGIC; 
  signal PCLK_Count_7_MC_D2_PT_0 : STD_LOGIC; 
  signal PCLK_Count_7_MC_D2_PT_1 : STD_LOGIC; 
  signal PCLK_Count_7_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_2_MC_Q : STD_LOGIC; 
  signal HSync_Count_2_MC_D : STD_LOGIC; 
  signal HSync_Count_2_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_2_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_2_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_2_MC_D1 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_3 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_4 : STD_LOGIC; 
  signal HSync_Count_2_MC_D2_PT_5 : STD_LOGIC; 
  signal HSync_Count_3_MC_Q : STD_LOGIC; 
  signal HSync_Count_3_MC_D : STD_LOGIC; 
  signal HSync_Count_3_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_3_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_3_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_3_MC_D1 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_0 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_1 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_2 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_3 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_4 : STD_LOGIC; 
  signal HSync_Count_3_MC_D2_PT_5 : STD_LOGIC; 
  signal HSync_Count_4_MC_Q : STD_LOGIC; 
  signal HSync_Count_4_MC_D : STD_LOGIC; 
  signal HSync_Count_4_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal HSync_Count_4_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal HSync_Count_4_MC_REG_tsimcreated_inv_FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal HSync_Count_4_MC_D1 : STD_LOGIC; 
  signal HSync_Count_4_MC_D2 : STD_LOGIC; 
  signal HSync_Count_4_MC_D2_PT_0 : STD_LOGIC;