vesa_vga_timesim.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim vesa_vga.nga vesa_vga_timesim.vhd 
-- Input file    : vesa_vga.nga
-- Output file   : vesa_vga_timesim.vhd
-- Design name   : vesa_vga.nga
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : XCR3256XL-10-PQ208 (Speed File: Version 6.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity vesa_vga is
  port (
    CLK : in STD_LOGIC := 'X'; 
    SET : in STD_LOGIC := 'X'; 
    UP : in STD_LOGIC := 'X'; 
    DE : out STD_LOGIC; 
    F_Byte : out STD_LOGIC; 
    F_G : out STD_LOGIC; 
    F_RP : out STD_LOGIC; 
    F_W : out STD_LOGIC; 
    HSync : out STD_LOGIC; 
    ODCK1X : out STD_LOGIC; 
    ODCK2X : out STD_LOGIC; 
    VSync : out STD_LOGIC; 
    F_DQ3 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    F_DQ1 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    F_DQ2 : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    B0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    B1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    F_A : out STD_LOGIC_VECTOR ( 21 downto 0 ); 
    F_E : out STD_LOGIC_VECTOR ( 3 downto 1 ); 
    G0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    G1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    R0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    R1 : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end vesa_vga;

architecture Structure of vesa_vga is
  signal F_DQ3_0_II_UIM : STD_LOGIC; 
  signal CLK_II_FCLK : STD_LOGIC; 
  signal SET_II_UIM : STD_LOGIC; 
  signal UP_II_UIM : STD_LOGIC; 
  signal F_DQ3_1_II_UIM : STD_LOGIC; 
  signal F_DQ3_2_II_UIM : STD_LOGIC; 
  signal F_DQ3_3_II_UIM : STD_LOGIC; 
  signal F_DQ3_4_II_UIM : STD_LOGIC; 
  signal F_DQ3_5_II_UIM : STD_LOGIC; 
  signal F_DQ3_6_II_UIM : STD_LOGIC; 
  signal F_DQ3_7_II_UIM : STD_LOGIC; 
  signal F_DQ3_8_II_UIM : STD_LOGIC; 
  signal F_DQ3_9_II_UIM : STD_LOGIC; 
  signal F_DQ3_10_II_UIM : STD_LOGIC; 
  signal F_DQ3_11_II_UIM : STD_LOGIC; 
  signal F_DQ3_12_II_UIM : STD_LOGIC; 
  signal F_DQ3_13_II_UIM : STD_LOGIC; 
  signal F_DQ3_14_II_UIM : STD_LOGIC; 
  signal F_DQ3_15_II_UIM : STD_LOGIC; 
  signal F_DQ1_0_II_UIM : STD_LOGIC; 
  signal F_DQ1_10_II_UIM : STD_LOGIC; 
  signal F_DQ1_11_II_UIM : STD_LOGIC; 
  signal F_DQ1_12_II_UIM : STD_LOGIC; 
  signal F_DQ1_13_II_UIM : STD_LOGIC; 
  signal F_DQ1_14_II_UIM : STD_LOGIC; 
  signal F_DQ1_15_II_UIM : STD_LOGIC; 
  signal F_DQ1_1_II_UIM : STD_LOGIC; 
  signal F_DQ1_2_II_UIM : STD_LOGIC; 
  signal F_DQ1_3_II_UIM : STD_LOGIC; 
  signal F_DQ1_4_II_UIM : STD_LOGIC; 
  signal F_DQ1_5_II_UIM : STD_LOGIC; 
  signal F_DQ1_6_II_UIM : STD_LOGIC; 
  signal F_DQ1_7_II_UIM : STD_LOGIC; 
  signal F_DQ1_8_II_UIM : STD_LOGIC; 
  signal F_DQ1_9_II_UIM : STD_LOGIC; 
  signal F_DQ2_0_II_UIM : STD_LOGIC; 
  signal F_DQ2_10_II_UIM : STD_LOGIC; 
  signal F_DQ2_11_II_UIM : STD_LOGIC; 
  signal F_DQ2_12_II_UIM : STD_LOGIC; 
  signal F_DQ2_13_II_UIM : STD_LOGIC; 
  signal F_DQ2_14_II_UIM : STD_LOGIC; 
  signal F_DQ2_15_II_UIM : STD_LOGIC; 
  signal F_DQ2_1_II_UIM : STD_LOGIC; 
  signal F_DQ2_2_II_UIM : STD_LOGIC; 
  signal F_DQ2_3_II_UIM : STD_LOGIC; 
  signal F_DQ2_4_II_UIM : STD_LOGIC; 
  signal F_DQ2_5_II_UIM : STD_LOGIC; 
  signal F_DQ2_6_II_UIM : STD_LOGIC; 
  signal F_DQ2_7_II_UIM : STD_LOGIC; 
  signal F_DQ2_8_II_UIM : STD_LOGIC; 
  signal F_DQ2_9_II_UIM : STD_LOGIC; 
  signal B0_0_MC_Q : STD_LOGIC; 
  signal B0_1_MC_Q : STD_LOGIC; 
  signal B0_2_MC_Q : STD_LOGIC; 
  signal B0_3_MC_Q : STD_LOGIC; 
  signal B0_4_MC_Q : STD_LOGIC; 
  signal B0_5_MC_Q : STD_LOGIC; 
  signal B0_6_MC_Q : STD_LOGIC; 
  signal B0_7_MC_Q : STD_LOGIC; 
  signal B1_0_MC_Q : STD_LOGIC; 
  signal B1_1_MC_Q : STD_LOGIC; 
  signal B1_2_MC_Q : STD_LOGIC; 
  signal B1_3_MC_Q : STD_LOGIC; 
  signal B1_4_MC_Q : STD_LOGIC; 
  signal B1_5_MC_Q : STD_LOGIC; 
  signal B1_6_MC_Q : STD_LOGIC; 
  signal B1_7_MC_Q : STD_LOGIC; 
  signal DE_MC_Q : STD_LOGIC; 
  signal F_A_0_MC_Q : STD_LOGIC; 
  signal F_A_10_MC_Q : STD_LOGIC; 
  signal F_A_11_MC_Q : STD_LOGIC; 
  signal F_A_12_MC_Q : STD_LOGIC; 
  signal F_A_13_MC_Q : STD_LOGIC; 
  signal F_A_14_MC_Q : STD_LOGIC; 
  signal F_A_15_MC_Q : STD_LOGIC; 
  signal F_A_16_MC_Q : STD_LOGIC; 
  signal F_A_17_MC_Q : STD_LOGIC; 
  signal F_A_18_MC_Q : STD_LOGIC; 
  signal F_A_19_MC_Q : STD_LOGIC; 
  signal F_A_1_MC_Q : STD_LOGIC; 
  signal F_A_20_MC_Q : STD_LOGIC; 
  signal F_A_21_MC_Q : STD_LOGIC; 
  signal F_A_2_MC_Q : STD_LOGIC; 
  signal F_A_3_MC_Q : STD_LOGIC; 
  signal F_A_4_MC_Q : STD_LOGIC; 
  signal F_A_5_MC_Q : STD_LOGIC; 
  signal F_A_6_MC_Q : STD_LOGIC; 
  signal F_A_7_MC_Q : STD_LOGIC; 
  signal F_A_8_MC_Q : STD_LOGIC; 
  signal F_A_9_MC_Q : STD_LOGIC; 
  signal F_Byte_MC_Q : STD_LOGIC; 
  signal F_E_1_MC_Q : STD_LOGIC; 
  signal F_E_2_MC_Q : STD_LOGIC; 
  signal F_E_3_MC_Q : STD_LOGIC; 
  signal F_G_MC_Q : STD_LOGIC; 
  signal F_RP_MC_Q : STD_LOGIC; 
  signal F_W_MC_Q : STD_LOGIC; 
  signal G0_0_MC_Q : STD_LOGIC; 
  signal G0_1_MC_Q : STD_LOGIC; 
  signal G0_2_MC_Q : STD_LOGIC; 
  signal G0_3_MC_Q : STD_LOGIC; 
  signal G0_4_MC_Q : STD_LOGIC; 
  signal G0_5_MC_Q : STD_LOGIC; 
  signal G0_6_MC_Q : STD_LOGIC; 
  signal G0_7_MC_Q : STD_LOGIC; 
  signal G1_0_MC_Q : STD_LOGIC; 
  signal G1_1_MC_Q : STD_LOGIC; 
  signal G1_2_MC_Q : STD_LOGIC; 
  signal G1_3_MC_Q : STD_LOGIC; 
  signal G1_4_MC_Q : STD_LOGIC; 
  signal G1_5_MC_Q : STD_LOGIC; 
  signal G1_6_MC_Q : STD_LOGIC; 
  signal G1_7_MC_Q : STD_LOGIC; 
  signal HSync_MC_Q : STD_LOGIC; 
  signal ODCK1X_MC_Q : STD_LOGIC; 
  signal ODCK2X_MC_Q : STD_LOGIC; 
  signal R0_0_MC_Q : STD_LOGIC; 
  signal R0_1_MC_Q : STD_LOGIC; 
  signal R0_2_MC_Q : STD_LOGIC; 
  signal R0_3_MC_Q : STD_LOGIC; 
  signal R0_4_MC_Q : STD_LOGIC; 
  signal R0_5_MC_Q : STD_LOGIC; 
  signal R0_6_MC_Q : STD_LOGIC; 
  signal R0_7_MC_Q : STD_LOGIC; 
  signal R1_0_MC_Q : STD_LOGIC; 
  signal R1_1_MC_Q : STD_LOGIC; 
  signal R1_2_MC_Q : STD_LOGIC; 
  signal R1_3_MC_Q : STD_LOGIC; 
  signal R1_4_MC_Q : STD_LOGIC; 
  signal R1_5_MC_Q : STD_LOGIC; 
  signal R1_6_MC_Q : STD_LOGIC; 
  signal R1_7_MC_Q : STD_LOGIC; 
  signal VSync_MC_Q : STD_LOGIC; 
  signal B0_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal B0_0_MC_D : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal B0_0_MC_D1 : STD_LOGIC; 
  signal B0_0_MC_D2 : STD_LOGIC; 
  signal ODCK1X_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal ODCK1X_MC_UIM : STD_LOGIC; 
  signal ODCK1X_MC_D : STD_LOGIC; 
  signal ODCK1X_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal FOOBAR4_ctinst_7 : STD_LOGIC; 
  signal ODCK1X_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal ODCK1X_MC_D1 : STD_LOGIC; 
  signal ODCK1X_MC_D2 : STD_LOGIC; 
  signal ODCK2X_MC_UIM : STD_LOGIC; 
  signal ODCK2X_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal ODCK2X_MC_D : STD_LOGIC; 
  signal ODCK2X_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal ODCK2X_MC_tsimcreated_prld_Q : STD_LOGIC; 
  signal ODCK2X_MC_D1 : STD_LOGIC; 
  signal ODCK2X_MC_D2 : STD_LOGIC; 
  signal SET_Deb_MC_Q : STD_LOGIC; 
  signal SET_Deb : STD_LOGIC; 
  signal SET_Deb_MC_D : STD_LOGIC; 
  signal SET_Deb_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal SET_Deb_MC_D1 : STD_LOGIC; 
  signal SET_Deb_MC_D2 : STD_LOGIC; 
  signal DLY_Deb : STD_LOGIC; 
  signal SET_D1 : STD_LOGIC; 
  signal SET_Deb_MC_D2_PT_0 : STD_LOGIC; 
  signal SET_D0 : STD_LOGIC; 
  signal SET_Deb_MC_D2_PT_1 : STD_LOGIC; 
  signal SET_D0_MC_Q : STD_LOGIC; 
  signal SET_D0_MC_D : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal SET_D0_MC_D1 : STD_LOGIC; 
  signal SET_D0_MC_D2 : STD_LOGIC; 
  signal DLY_Deb_MC_Q : STD_LOGIC; 
  signal DLY_Deb_MC_D : STD_LOGIC; 
  signal DLY_Deb_MC_D1 : STD_LOGIC; 
  signal DLY_Deb_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_21_MC_Q : STD_LOGIC; 
  signal CLK_Deb_21_MC_D : STD_LOGIC; 
  signal CLK_Deb_21_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_21_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_21_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_0_MC_Q : STD_LOGIC; 
  signal CLK_Deb_0_MC_D : STD_LOGIC; 
  signal CLK_Deb_0_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_0_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_0_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_10_MC_Q : STD_LOGIC; 
  signal CLK_Deb_10_MC_D : STD_LOGIC; 
  signal CLK_Deb_10_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_10_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_10_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_1_MC_Q : STD_LOGIC; 
  signal CLK_Deb_1_MC_D : STD_LOGIC; 
  signal CLK_Deb_1_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_1_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_1_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_2_MC_Q : STD_LOGIC; 
  signal CLK_Deb_2_MC_D : STD_LOGIC; 
  signal CLK_Deb_2_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_2_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_2_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_3_MC_Q : STD_LOGIC; 
  signal CLK_Deb_3_MC_D : STD_LOGIC; 
  signal CLK_Deb_3_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_3_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_3_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_4_MC_Q : STD_LOGIC; 
  signal CLK_Deb_4_MC_D : STD_LOGIC; 
  signal CLK_Deb_4_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_4_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_4_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_5_MC_Q : STD_LOGIC; 
  signal CLK_Deb_5_MC_D : STD_LOGIC; 
  signal CLK_Deb_5_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_5_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_5_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_6_MC_Q : STD_LOGIC; 
  signal CLK_Deb_6_MC_D : STD_LOGIC; 
  signal CLK_Deb_6_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_6_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_6_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_7_MC_Q : STD_LOGIC; 
  signal CLK_Deb_7_MC_D : STD_LOGIC; 
  signal CLK_Deb_7_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_7_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_7_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_8_MC_Q : STD_LOGIC; 
  signal CLK_Deb_8_MC_D : STD_LOGIC; 
  signal CLK_Deb_8_MC_tsimcreated_xor_Q : STD_LOGIC; 
  signal CLK_Deb_8_MC_D1 : STD_LOGIC; 
  signal CLK_Deb_8_MC_D2 : STD_LOGIC; 
  signal CLK_Deb_9_MC_Q : STD_LOGIC;