📄 am29lv160d.v
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parameter SubSecNum = 3;
parameter HiAddrBit = 19;
parameter MemSize = (SecNum+1) *(SecSize+1)-1;
//varaibles to resolve if bottom or top architecture is used
reg [20*8-1:0] tmp_timing;//stores copy of TimingModel
reg [20*8-1:0] tmp1_timing;//stores copy of TimingModel
reg [7:0] tmp_char;//stores "t" or "b" character
integer found = 1'b0;
// powerup
reg PoweredUp;
//FSM control signals
reg ULBYPASS ; ////Unlock Bypass Active
reg ESP_ACT ; ////Erase Suspend
reg PDONE ; ////Prog. Done
reg PSTART ; ////Start Programming
//Program location is in protected sector
reg PERR ;
reg EDONE ; ////Ers. Done
reg ESTART ; ////Start Erase
reg ESUSP ; ////Suspend Erase
reg ERES ; ////Resume Erase
//All sectors selected for erasure are protected
reg EERR ;
//Sectors selected for erasure
reg [SecNum:0] Ers_queue; // = SecNum'b0;
reg [SubSecNum:0] Ers_sub_queue;
//Command Register
reg write ;
reg read ;
//Sector Address
integer SecAddr = 0; // 0 - SecNum
integer SubSect = 0; // 0 - SubSecNum
integer SA = 0; // 0 TO SecNum
integer SSA = 0; // 0 TO SubSecNum
//Address within sector
integer Address = 0; // 0 - SecSize
integer D_tmp0; //0 TO MaxData;
integer D_tmp1; //0 TO MaxData;
//A19:A11 Don't Care
integer Addr ; //0 TO 16'h7FF#
//glitch protection
wire gWE_n ;
wire gCE_n ;
wire gOE_n ;
reg RST ;
reg reseted ;
integer Mem[0:MemSize];
//Sector Protection Status
reg [SecNum:0] Sec_Prot; //= SecNum'b0;
//Sector Protection for first 4 sectors
//or last 4, depending on chosen model
reg [SubSecNum:0] SubSec_Prot;
integer CFI_array[16:90];
// timing check violation
reg Viol = 1'b0;
//Address of variable size sector (bottom or top boot sector)
integer VarSect = -1;
reg vs;
integer WBData[0:1];
integer WBAddr[0:1];
reg oe = 1'b0;
event oe_event;
event initOK;
event MergeE;
//Status reg.
reg[7:0] Status = 8'b0;
reg[7:0] old_bit, new_bit;
integer old_int, new_int;
integer wr_cnt;
integer S_ind = 0;
integer ind = 0;
reg[7:0] temp;
integer i,j,k;
//TPD_XX_DATA
time OEDQ_t;
time CEDQ_t;
time OENeg_event;
time CENeg_event;
reg FROMOE;
reg FROMCE;
reg SWITCH;
integer OEDQ_01;
integer CEDQ_01;
///////////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////////
buf (A19_ipd, A19);
buf (A18_ipd, A18);
buf (A17_ipd, A17);
buf (A16_ipd, A16);
buf (A15_ipd, A15);
buf (A14_ipd, A14);
buf (A13_ipd, A13);
buf (A12_ipd, A12);
buf (A11_ipd, A11);
buf (A10_ipd, A10);
buf (A9_ipd , A9 );
buf (A8_ipd , A8 );
buf (A7_ipd , A7 );
buf (A6_ipd , A6 );
buf (A5_ipd , A5 );
buf (A4_ipd , A4 );
buf (A3_ipd , A3 );
buf (A2_ipd , A2 );
buf (A1_ipd , A1 );
buf (A0_ipd , A0 );
buf (DQ15_ipd, DQ15);
buf (DQ14_ipd, DQ14);
buf (DQ13_ipd, DQ13);
buf (DQ12_ipd, DQ12);
buf (DQ11_ipd, DQ11);
buf (DQ10_ipd, DQ10);
buf (DQ9_ipd , DQ9 );
buf (DQ8_ipd , DQ8 );
buf (DQ7_ipd , DQ7 );
buf (DQ6_ipd , DQ6 );
buf (DQ5_ipd , DQ5 );
buf (DQ4_ipd , DQ4 );
buf (DQ3_ipd , DQ3 );
buf (DQ2_ipd , DQ2 );
buf (DQ1_ipd , DQ1 );
buf (DQ0_ipd , DQ0 );
buf (CENeg_ipd , CENeg );
buf (OENeg_ipd , OENeg );
buf (WENeg_ipd , WENeg );
buf (RESETNeg_ipd , RESETNeg );
buf (BYTENeg_ipd , BYTENeg );
///////////////////////////////////////////////////////////////////////////////
// Propagation delay Section
///////////////////////////////////////////////////////////////////////////////
nmos (DQ15, DQ15_zd , 1);
nmos (DQ14, DQ14_zd , 1);
nmos (DQ13, DQ13_zd , 1);
nmos (DQ12, DQ12_zd , 1);
nmos (DQ11, DQ11_zd , 1);
nmos (DQ10, DQ10_zd , 1);
nmos (DQ9 , DQ9_zd , 1);
nmos (DQ8 , DQ8_zd , 1);
nmos (DQ7 , DQ7_zd , 1);
nmos (DQ6 , DQ6_zd , 1);
nmos (DQ5 , DQ5_zd , 1);
nmos (DQ4 , DQ4_zd , 1);
nmos (DQ3 , DQ3_zd , 1);
nmos (DQ2 , DQ2_zd , 1);
nmos (DQ1 , DQ1_zd , 1);
nmos (DQ0 , DQ0_zd , 1);
nmos (RY , 1'b0 , ~RY_zd);
wire deg;
specify
// tipd delays: interconnect path delays , mapped to input port delays.
// In Verilog is not necessary to declare any tipd_ delay variables,
// they can be taken from SDF file
// With all the other delays real delays would be taken from SDF file
// tpd delays
specparam tpd_A0_DQ0 =1;
specparam tpd_A0_DQ1 =1;
specparam tpd_A0_DQ2 =1;
specparam tpd_A0_DQ3 =1;
specparam tpd_A0_DQ4 =1;
specparam tpd_A0_DQ5 =1;
specparam tpd_A0_DQ6 =1;
specparam tpd_A0_DQ7 =1;
specparam tpd_A0_DQ8 =1;
specparam tpd_A0_DQ9 =1;
specparam tpd_A0_DQ10 =1;
specparam tpd_A0_DQ11 =1;
specparam tpd_A0_DQ12 =1;
specparam tpd_A0_DQ13 =1;
specparam tpd_A0_DQ14 =1;
specparam tpd_A0_DQ15 =1;
specparam tpd_A1_DQ0 =1;
specparam tpd_A1_DQ1 =1;
specparam tpd_A1_DQ2 =1;
specparam tpd_A1_DQ3 =1;
specparam tpd_A1_DQ4 =1;
specparam tpd_A1_DQ5 =1;
specparam tpd_A1_DQ6 =1;
specparam tpd_A1_DQ7 =1;
specparam tpd_A1_DQ8 =1;
specparam tpd_A1_DQ9 =1;
specparam tpd_A1_DQ10 =1;
specparam tpd_A1_DQ11 =1;
specparam tpd_A1_DQ12 =1;
specparam tpd_A1_DQ13 =1;
specparam tpd_A1_DQ14 =1;
specparam tpd_A1_DQ15 =1;
specparam tpd_A2_DQ0 =1;
specparam tpd_A2_DQ1 =1;
specparam tpd_A2_DQ2 =1;
specparam tpd_A2_DQ3 =1;
specparam tpd_A2_DQ4 =1;
specparam tpd_A2_DQ5 =1;
specparam tpd_A2_DQ6 =1;
specparam tpd_A2_DQ7 =1;
specparam tpd_A2_DQ8 =1;
specparam tpd_A2_DQ9 =1;
specparam tpd_A2_DQ10 =1;
specparam tpd_A2_DQ11 =1;
specparam tpd_A2_DQ12 =1;
specparam tpd_A2_DQ13 =1;
specparam tpd_A2_DQ14 =1;
specparam tpd_A2_DQ15 =1;
specparam tpd_A3_DQ0 =1;
specparam tpd_A3_DQ1 =1;
specparam tpd_A3_DQ2 =1;
specparam tpd_A3_DQ3 =1;
specparam tpd_A3_DQ4 =1;
specparam tpd_A3_DQ5 =1;
specparam tpd_A3_DQ6 =1;
specparam tpd_A3_DQ7 =1;
specparam tpd_A3_DQ8 =1;
specparam tpd_A3_DQ9 =1;
specparam tpd_A3_DQ10 =1;
specparam tpd_A3_DQ11 =1;
specparam tpd_A3_DQ12 =1;
specparam tpd_A3_DQ13 =1;
specparam tpd_A3_DQ14 =1;
specparam tpd_A3_DQ15 =1;
specparam tpd_A4_DQ0 =1;
specparam tpd_A4_DQ1 =1;
specparam tpd_A4_DQ2 =1;
specparam tpd_A4_DQ3 =1;
specparam tpd_A4_DQ4 =1;
specparam tpd_A4_DQ5 =1;
specparam tpd_A4_DQ6 =1;
specparam tpd_A4_DQ7 =1;
specparam tpd_A4_DQ8 =1;
specparam tpd_A4_DQ9 =1;
specparam tpd_A4_DQ10 =1;
specparam tpd_A4_DQ11 =1;
specparam tpd_A4_DQ12 =1;
specparam tpd_A4_DQ13 =1;
specparam tpd_A4_DQ14 =1;
specparam tpd_A4_DQ15 =1;
specparam tpd_A5_DQ0 =1;
specparam tpd_A5_DQ1 =1;
specparam tpd_A5_DQ2 =1;
specparam tpd_A5_DQ3 =1;
specparam tpd_A5_DQ4 =1;
specparam tpd_A5_DQ5 =1;
specparam tpd_A5_DQ6 =1;
specparam tpd_A5_DQ7 =1;
specparam tpd_A5_DQ8 =1;
specparam tpd_A5_DQ9 =1;
specparam tpd_A5_DQ10 =1;
specparam tpd_A5_DQ11 =1;
specparam tpd_A5_DQ12 =1;
specparam tpd_A5_DQ13 =1;
specparam tpd_A5_DQ14 =1;
specparam tpd_A5_DQ15 =1;
specparam tpd_A6_DQ0 =1;
specparam tpd_A6_DQ1 =1;
specparam tpd_A6_DQ2 =1;
specparam tpd_A6_DQ3 =1;
specparam tpd_A6_DQ4 =1;
specparam tpd_A6_DQ5 =1;
specparam tpd_A6_DQ6 =1;
specparam tpd_A6_DQ7 =1;
specparam tpd_A6_DQ8 =1;
specparam tpd_A6_DQ9 =1;
specparam tpd_A6_DQ10 =1;
specparam tpd_A6_DQ11 =1;
specparam tpd_A6_DQ12 =1;
specparam tpd_A6_DQ13 =1;
specparam tpd_A6_DQ14 =1;
specparam tpd_A6_DQ15 =1;
specparam tpd_A7_DQ0 =1;
specparam tpd_A7_DQ1 =1;
specparam tpd_A7_DQ2 =1;
specparam tpd_A7_DQ3 =1;
specparam tpd_A7_DQ4 =1;
specparam tpd_A7_DQ5 =1;
specparam tpd_A7_DQ6 =1;
specparam tpd_A7_DQ7 =1;
specparam tpd_A7_DQ8 =1;
specparam tpd_A7_DQ9 =1;
specparam tpd_A7_DQ10 =1;
specparam tpd_A7_DQ11 =1;
specparam tpd_A7_DQ12 =1;
specparam tpd_A7_DQ13 =1;
specparam tpd_A7_DQ14 =1;
specparam tpd_A7_DQ15 =1;
specparam tpd_A8_DQ0 =1;
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