systemtb.vhd

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

-- =================================
--	System Test Bench
-- =================================
library ieee;
use ieee.std_logic_1164.all;

entity SystemTB is
end;

architecture SystemTB_b of SystemTB is
	component am29lv160d
		port(
    		A19:in std_logic;
    		A18:in std_logic;
    		A17:in std_logic;
    		A16:in std_logic;
	    A15:in std_logic;
    	    A14:in std_logic;
	     A13:in std_logic;
	     A12:in std_logic;
	     A11:in std_logic;
	     A10:in std_logic;
    		A9 :in std_logic;
    		A8 :in std_logic;
    		A7 :in std_logic;
    		A6 :in std_logic;
    		A5 :in std_logic;
    		A4 :in std_logic;
    		A3 :in std_logic;
    		A2 :in std_logic;
    		A1 :in std_logic;
    		A0 :in std_logic;
           
    		DQ15 :inout std_logic;
    		DQ14 :inout std_logic;
    		DQ13 :inout std_logic;
    		DQ12 :inout std_logic;
    		DQ11 :inout std_logic;
    		DQ10 :inout std_logic;
    		DQ9  :inout std_logic;
    		DQ8  :inout std_logic;
    		DQ7  :inout std_logic;
    		DQ6  :inout std_logic;
    		DQ5  :inout std_logic;
    		DQ4  :inout std_logic;
    		DQ3  :inout std_logic;
    		DQ2  :inout std_logic;
    		DQ1  :inout std_logic;
    		DQ0  :inout std_logic;
           
    		CENeg    :in std_logic;
    		OENeg    :in std_logic;
    		WENeg    :in std_logic;
    		RESETNeg :in std_logic;
    		BYTENeg  :in std_logic;
    		RY       :out std_logic);
	end component;

	component vesa_vga
		port(
			-- // Board Control ----------------
			SET:in std_logic;	-- Start Enabled Signal(edge)
			UP: in std_logic;
			-- // Signal -----------------------
			CLK:in std_logic;	-- CLOCK
			HSync: out std_logic;
			VSync: out std_logic;
			DE: out std_logic;
			ODCK1X: out std_logic;
			ODCK2X: out std_logic;
			R0: out std_logic_vector(7 downto 0);
			R1: out std_logic_vector(7 downto 0);
			G0: out std_logic_vector(7 downto 0);
			G1: out std_logic_vector(7 downto 0);
			B0: out std_logic_vector(7 downto 0);
			B1: out std_logic_vector(7 downto 0);
		-- // Flash Control --------------
			F_A: out std_logic_vector(21 downto 0);
			F_DQ1: in std_logic_vector(15 downto 0);
			F_DQ2: in std_logic_vector(15 downto 0);
			F_DQ3: in std_logic_vector(15 downto 0);
			F_E: out std_logic_vector(3 downto 1);	-- chip enable(0 for enable)
			F_G: out std_logic;				-- output enable(0 for enable)
			F_W: out std_logic;				-- write enable(0 for enable)
			F_Byte: out std_logic;			-- byte(0)/word(1) select
			F_RP: out std_logic				-- Reset/Block Temporary Unprotect
			--F_RB: in std_logic			-- ready/busy state 
		);
	end component;
	
	signal clock: std_logic := '0';
	signal start: std_logic := '0';
	signal ups: std_logic := '0';
	signal HSyncs,VSyncs,ODCK1Xs,ODCK2Xs,DEs :std_logic := '0';
	signal R0s: std_logic_vector(7 downto 0);
	signal R1s: std_logic_vector(7 downto 0);
	signal G0s: std_logic_vector(7 downto 0);
	signal G1s: std_logic_vector(7 downto 0);
	signal B0s: std_logic_vector(7 downto 0);
	signal B1s: std_logic_vector(7 downto 0);

	signal F_Addr: std_logic_vector(21 downto 0);
 	signal F_Data1: std_logic_vector(15 downto 0);
	signal F_Data2: std_logic_vector(15 downto 0);
	signal F_Data3: std_logic_vector(15 downto 0);
	signal F_E_B: std_logic_vector(3 downto 1);	 -- chip enable(0 for enable)
	signal F_G_B: std_logic;			-- output enable(0 for enable)
	signal F_W_B: std_logic;		-- write enable(0 for enable)
	signal F_Byte_B: std_logic;		-- byte(0)/word(1) select
	signal F_RB_B: std_logic;	-- ready/busy state
	signal F_RP_B: std_logic;	-- Reset/Block Temporary Unprotect

begin
	UUT: vesa_vga port map(SET=> start, UP=> ups, CLK => clock, 
			HSync => HSyncs, VSync => VSyncs, DE => DEs,
			ODCK1X => ODCK1Xs, ODCK2X => ODCK2Xs,
			R0 => R0s, R1 => R1s,
			G0 => G0s, G1 => G1s,
			B0 => B0s, B1 => B1s,
			F_A => F_Addr,
			F_DQ1 => F_Data1,
			F_DQ2 => F_Data2,
			F_DQ3 => F_Data3,
			F_E => F_E_B,
			F_G => F_G_B,
			F_W => F_W_B,
			F_Byte => F_Byte_B,
			F_RP => F_RP_B);
	
	start <= '1' after 150 ms;
	ups <= '1' after 100 ns;		
	process begin
		wait for 9 ns;
		clock <= not clock;
	end process;

	UUT1: am29lv160d port map(A19 => F_Addr(19),A18 => F_Addr(18),A17 => F_Addr(17),
    		A16 => F_Addr(16),A15 => F_Addr(15),A14 => F_Addr(14),A13 => F_Addr(13),
	     A12 => F_Addr(12),A11 => F_Addr(11),A10 => F_Addr(10),A9  => F_Addr(9),
    		A8  => F_Addr(8),A7  => F_Addr(7),A6  => F_Addr(6),A5  => F_Addr(5),
    		A4  => F_Addr(4),A3  => F_Addr(3),A2  => F_Addr(2),A1  => F_Addr(1),
    		A0  => F_Addr(0),
           
    		DQ15 => F_Data1(15),
    		DQ14 => F_Data1(14),
    		DQ13 => F_Data1(13),
    		DQ12 => F_Data1(12),
    		DQ11 => F_Data1(11),
    		DQ10 => F_Data1(10),
    		DQ9  => F_Data1(9),
    		DQ8  => F_Data1(8),
    		DQ7  => F_Data1(7),
    		DQ6  => F_Data1(6),
    		DQ5  => F_Data1(5),
    		DQ4  => F_Data1(4),
    		DQ3  => F_Data1(3),
    		DQ2  => F_Data1(2),
    		DQ1  => F_Data1(1),
    		DQ0  => F_Data1(0),
           
    		CENeg => F_E_B(1),	OENeg => F_G_B,	WENeg => F_W_B,
    		RESETNeg  => F_RP_B,BYTENeg => F_Byte_B, RY=> F_RB_B);

	UUT2: am29lv160d port map(A19 => F_Addr(19),A18 => F_Addr(18),A17 => F_Addr(17),
    		A16 => F_Addr(16),A15 => F_Addr(15),A14 => F_Addr(14),A13 => F_Addr(13),
	     A12 => F_Addr(12),A11 => F_Addr(11),A10 => F_Addr(10),A9  => F_Addr(9),
    		A8  => F_Addr(8),A7  => F_Addr(7),A6  => F_Addr(6),A5  => F_Addr(5),
    		A4  => F_Addr(4),A3  => F_Addr(3),A2  => F_Addr(2),A1  => F_Addr(1),
    		A0  => F_Addr(0),
           
    		DQ15 => F_Data2(15),
    		DQ14 => F_Data2(14),
    		DQ13 => F_Data2(13),
    		DQ12 => F_Data2(12),
    		DQ11 => F_Data2(11),
    		DQ10 => F_Data2(10),
    		DQ9  => F_Data2(9),
    		DQ8  => F_Data2(8),
    		DQ7  => F_Data2(7),
    		DQ6  => F_Data2(6),
    		DQ5  => F_Data2(5),
    		DQ4  => F_Data2(4),
    		DQ3  => F_Data2(3),
    		DQ2  => F_Data2(2),
    		DQ1  => F_Data2(1),
    		DQ0  => F_Data2(0),
           
    		CENeg => F_E_B(2),	OENeg => F_G_B,	WENeg => F_W_B,
    		RESETNeg  => F_RP_B,BYTENeg => F_Byte_B, RY=> F_RB_B);

	UUT3: am29lv160d port map(A19 => F_Addr(19),A18 => F_Addr(18),A17 => F_Addr(17),
    		A16 => F_Addr(16),A15 => F_Addr(15),A14 => F_Addr(14),A13 => F_Addr(13),
	     A12 => F_Addr(12),A11 => F_Addr(11),A10 => F_Addr(10),A9  => F_Addr(9),
    		A8  => F_Addr(8),A7  => F_Addr(7),A6  => F_Addr(6),A5  => F_Addr(5),
    		A4  => F_Addr(4),A3  => F_Addr(3),A2  => F_Addr(2),A1  => F_Addr(1),
    		A0  => F_Addr(0),
           
    		DQ15 => F_Data3(15),
    		DQ14 => F_Data3(14),
    		DQ13 => F_Data3(13),
    		DQ12 => F_Data3(12),
    		DQ11 => F_Data3(11),
    		DQ10 => F_Data3(10),
    		DQ9  => F_Data3(9),
    		DQ8  => F_Data3(8),
    		DQ7  => F_Data3(7),
    		DQ6  => F_Data3(6),
    		DQ5  => F_Data3(5),
    		DQ4  => F_Data3(4),
    		DQ3  => F_Data3(3),
    		DQ2  => F_Data3(2),
    		DQ1  => F_Data3(1),
    		DQ0  => F_Data3(0),
           
    		CENeg => F_E_B(3),	OENeg => F_G_B,	WENeg => F_W_B,
    		RESETNeg  => F_RP_B,BYTENeg => F_Byte_B, RY=> F_RB_B);

end;