_info

本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證

m255
cModel Technology
dE:\WorkingFile\MiniPG\MVHDL
vam29lv160d
INQEZeJTB:j<K^_<?H::Sk0
VM>fW=ER2NBZH;QoAPFhHD3
dD:\WorkingFile\MiniPG\MVHDL
w1096601016
FD:/WorkingFile/MiniPG/MVHDL/am29lv160d.v
L0 59
OE;L;5.7g;17
r1
31
o-work work
Esystemtb
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1119126858
dD:\WorkingFile\MiniPG\MVHDL
FD:/WorkingFile/MiniPG/MVHDL/SystemTB.vhd
l0
L7
V0;e2z>6k90N7EN:J[NzO00
OE;C;5.7g;15
o-work work -87 -explicit
tExplicit T
Asystemtb_b
DP verilog vl_types 4Il9Q]^f[N5<2oIJc<A_>3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3
DP simprim vpackage UR>AzNzXHk:<[LgoB?o`A1
DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0
DP simprim vcomponents UlVl4g0PHOHBHh?Z41Qe03
DE work am29lv160d M>fW=ER2NBZH;QoAPFhHD3
DE work vesa_vga 7T_B6bQm4dII2>coLzcLE3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work systemtb 0;e2z>6k90N7EN:J[NzO00
l113
L10
Vk><JY6FRFb@=T48h;Oiaz2
OE;C;5.7g;15
M7 ieee std_logic_1164
M6 simprim vcomponents
M5 vital2000 vital_timing
M4 simprim vpackage
M3 vital2000 vital_primitives
M2 std textio
M1 verilog vl_types
o-work work -87 -explicit
tExplicit T
Evesa_vga
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3
DP simprim vpackage UR>AzNzXHk:<[LgoB?o`A1
DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0
DP simprim vcomponents UlVl4g0PHOHBHh?Z41Qe03
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1119212120
dD:\WorkingFile\MiniPG\MVHDL
FD:/WorkingFile/MiniPG/MVHDL/vesa_vga_timesim.vhd
l0
L22
V7T_B6bQm4dII2>coLzcLE3
OE;C;5.7g;15
o-work work -87 -explicit
tExplicit T
Astructure
DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DE simprim x_roc h7QPjGgL<bNb3[Gli3z;a1
DE simprim x_or32 <fJ7CzDXX7ZMW8OoWAQEb0
DE simprim x_or3 o9nTaQE>6EzTOl_4l;b_=0
DE simprim x_inv k]WfT4nk10LehOI:JGmHH0
DE simprim x_or16 2zb3aGfD9PkQNEZYRA6Ae3
DE simprim x_and8 176:9nV@jV^18hm?2X9_k1
DE simprim x_and7 TMmgB[8b0=zVI9hj1VWC>2
DE simprim x_and6 lDhc9_@E1R9RbBVY9ELIT3
DE simprim x_and3 :l;Z6NaT7AS:hB78:g`zz0
DE simprim x_and16 YL[YhJJ7a5UQUhk8@85D?0
DE simprim x_and32 ZTL51bWaGjBdKL8^LeojW3
DE simprim x_and5 :^l9?5jj7l@0?Lofz[BmS0
DE simprim x_and4 2`@7I:Z8VNh0nY[2FJO3Y1
DE simprim x_or2 gB=z`ehg@8G6kJ>?2<QO]1
DE simprim x_and2 QSH7F5]gmKjT97[S0?DgL0
DE simprim x_xor2 W;4I9cIPMoTc2;F>8Y@641
DE simprim x_one <D0K;n7QZV15LdUciA[nB2
DE simprim x_zero N^U=T=[a8c=0?VcPXJKkl3
DE simprim x_ff oAPf5n9MCEIhWDHKaDAKM2
DE simprim x_buf g>zldXRLeD9S;Mi<MUBN:1
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3
DP simprim vpackage UR>AzNzXHk:<[LgoB?o`A1
DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0
DP simprim vcomponents UlVl4g0PHOHBHh?Z41Qe03
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work vesa_vga 7T_B6bQm4dII2>coLzcLE3
l1480
L50
V_kiK9<^9<UaVF^:Y1Yz=E1
OE;C;5.7g;15
M9 ieee std_logic_1164
M8 simprim vcomponents
M7 vital2000 vital_timing
M6 simprim vpackage
M5 vital2000 vital_primitives
M4 std textio
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee vital_timing
o-work work -87 -explicit
tExplicit T
Avesa_vga_bh
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work vesa_vga d=i^hK8RoPk6JNHRY4l4P2
l58
L23
VThF5Y3EI5Uc0L888zzUOC3
OE;C;5.7g;15
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-work work -87 -explicit
tExplicit T
FE:/WorkingFile/MiniPG/MVHDL/VESA_VGA.vhd
w1118887838
dE:\WorkingFile\MiniPG\MVHDL
Avesa_vga
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work vesa_vga d=i^hK8RoPk6JNHRY4l4P2
l91
L41
VcceT9hR56P?9c1>bUJ_Ci3
OE;C;5.7g;15
M3 ieee std_logic_1164
M2 ieee std_logic_unsigned
M1 ieee std_logic_arith
o-work work -87 -explicit
tExplicit T
w1118884494
FE:/WorkingFile/MiniPG/MVHDL/VESA_VGA.vhd
dE:\WorkingFile\MiniPG\MVHDL
vVITALbuf
IjJPM047<6eN2U7JEYGSfn2
VFm^LTC8OBQB_cL`YSe2R93
dD:\WorkingFile\MiniPG\MVHDL
w1096601016
FD:/WorkingFile/MiniPG/MVHDL/am29lv160d.v
L0 3655
OE;L;5.7g;17
r1
31
o-work work
n@v@i@t@a@lbuf