lcd1602.tan.qmsg

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "LCD_Data\[4\]~reg0 Reset Clk 3.900 ns register " "Info: th for register \"LCD_Data\[4\]~reg0\" (data pin = \"Reset\", clock pin = \"Clk\") is 3.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 9.900 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns Clk 1 CLK PIN_87 22 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 22; CLK Node = 'Clk'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Clk } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "2.500 ns" { Clk Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns LCD_Data\[4\]~reg0 3 REG LC16 4 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC16; Fanout = 4; REG Node = 'LCD_Data\[4\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "4.900 ns" { Clk_Out LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[4]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns Reset 1 PIN PIN_37 70 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 70; PIN Node = 'Reset'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Reset } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 7.300 ns LCD_Data\[4\]~reg0 2 REG LC16 4 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 7.300 ns; Loc. = LC16; Fanout = 4; REG Node = 'LCD_Data\[4\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "5.900 ns" { Reset LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 61.64 % " "Info: Total cell delay = 4.500 ns ( 61.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 38.36 % " "Info: Total interconnect delay = 2.800 ns ( 38.36 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "7.300 ns" { Reset LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.300 ns" { Reset Reset~out LCD_Data[4]~reg0 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 3.100ns } } }  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[4]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "7.300 ns" { Reset LCD_Data[4]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.300 ns" { Reset Reset~out LCD_Data[4]~reg0 } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 3.100ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:57:30 2007 " "Info: Processing ended: Thu Jul 05 23:57:30 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}