lcd1602.tan.qmsg

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Clk_Out " "Info: Detected ripple clock \"Clk_Out\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Clk_Out" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Current_State~41 register LCD_Data\[0\]~reg0 70.92 MHz 14.1 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 70.92 MHz between source register \"Current_State~41\" and destination register \"LCD_Data\[0\]~reg0\" (period= 14.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.600 ns + Longest register register " "Info: + Longest register to register delay is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Current_State~41 1 REG LC121 52 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC121; Fanout = 52; REG Node = 'Current_State~41'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Current_State~41 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.800 ns) 6.500 ns LCD_Data\[0\]~104 2 COMB SEXP4 4 " "Info: 2: + IC(2.700 ns) + CELL(3.800 ns) = 6.500 ns; Loc. = SEXP4; Fanout = 4; COMB Node = 'LCD_Data\[0\]~104'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "6.500 ns" { Current_State~41 LCD_Data[0]~104 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 9.600 ns LCD_Data\[0\]~reg0 3 REG LC9 3 " "Info: 3: + IC(0.000 ns) + CELL(3.100 ns) = 9.600 ns; Loc. = LC9; Fanout = 3; REG Node = 'LCD_Data\[0\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "3.100 ns" { LCD_Data[0]~104 LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 71.88 % " "Info: Total cell delay = 6.900 ns ( 71.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 28.13 % " "Info: Total interconnect delay = 2.700 ns ( 28.13 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.600 ns" { Current_State~41 LCD_Data[0]~104 LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.600 ns" { Current_State~41 LCD_Data[0]~104 LCD_Data[0]~reg0 } { 0.000ns 2.700ns 0.000ns } { 0.000ns 3.800ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 9.900 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns Clk 1 CLK PIN_87 22 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 22; CLK Node = 'Clk'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Clk } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "2.500 ns" { Clk Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns LCD_Data\[0\]~reg0 3 REG LC9 3 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC9; Fanout = 3; REG Node = 'LCD_Data\[0\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "4.900 ns" { Clk_Out LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[0]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 9.900 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns Clk 1 CLK PIN_87 22 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 22; CLK Node = 'Clk'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Clk } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "2.500 ns" { Clk Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns Current_State~41 3 REG LC121 52 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC121; Fanout = 52; REG Node = 'Current_State~41'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "4.900 ns" { Clk_Out Current_State~41 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out Current_State~41 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out Current_State~41 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[0]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out Current_State~41 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out Current_State~41 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.600 ns" { Current_State~41 LCD_Data[0]~104 LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.600 ns" { Current_State~41 LCD_Data[0]~104 LCD_Data[0]~reg0 } { 0.000ns 2.700ns 0.000ns } { 0.000ns 3.800ns 3.100ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[0]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out Current_State~41 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out Current_State~41 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "Clk_Out Reset Clk 5.000 ns register " "Info: tsu for register \"Clk_Out\" (data pin = \"Reset\", clock pin = \"Clk\") is 5.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Longest pin register " "Info: + Longest pin to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns Reset 1 PIN PIN_37 70 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 70; PIN Node = 'Reset'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Reset } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.300 ns) 5.500 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(2.800 ns) + CELL(1.300 ns) = 5.500 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "4.100 ns" { Reset Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.700 ns 49.09 % " "Info: Total cell delay = 2.700 ns ( 49.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 50.91 % " "Info: Total interconnect delay = 2.800 ns ( 50.91 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "5.500 ns" { Reset Clk_Out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { Reset Reset~out Clk_Out } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns Clk 1 CLK PIN_87 22 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 22; CLK Node = 'Clk'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Clk } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "0.900 ns" { Clk Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "3.400 ns" { Clk Clk_Out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { Clk Clk~out Clk_Out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "5.500 ns" { Reset Clk_Out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { Reset Reset~out Clk_Out } { 0.000ns 0.000ns 2.800ns } { 0.000ns 1.400ns 1.300ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "3.400 ns" { Clk Clk_Out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { Clk Clk~out Clk_Out } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk LCD_Data\[1\] LCD_Data\[1\]~reg0 13.100 ns register " "Info: tco from clock \"Clk\" to destination pin \"LCD_Data\[1\]\" through register \"LCD_Data\[1\]~reg0\" is 13.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 9.900 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns Clk 1 CLK PIN_87 22 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 22; CLK Node = 'Clk'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { Clk } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns Clk_Out 2 REG LC8 16 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC8; Fanout = 16; REG Node = 'Clk_Out'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "2.500 ns" { Clk Clk_Out } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.200 ns) 9.900 ns LCD_Data\[1\]~reg0 3 REG LC11 3 " "Info: 3: + IC(2.700 ns) + CELL(2.200 ns) = 9.900 ns; Loc. = LC11; Fanout = 3; REG Node = 'LCD_Data\[1\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "4.900 ns" { Clk_Out LCD_Data[1]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 72.73 % " "Info: Total cell delay = 7.200 ns ( 72.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 27.27 % " "Info: Total interconnect delay = 2.700 ns ( 27.27 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[1]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_Data\[1\]~reg0 1 REG LC11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 3; REG Node = 'LCD_Data\[1\]~reg0'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "" { LCD_Data[1]~reg0 } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns LCD_Data\[1\] 2 PIN PIN_96 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'LCD_Data\[1\]'" {  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "1.600 ns" { LCD_Data[1]~reg0 LCD_Data[1] } "NODE_NAME" } "" } } { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns 100.00 % " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "1.600 ns" { LCD_Data[1]~reg0 LCD_Data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { LCD_Data[1]~reg0 LCD_Data[1] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "9.900 ns" { Clk Clk_Out LCD_Data[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.900 ns" { Clk Clk~out Clk_Out LCD_Data[1]~reg0 } { 0.000ns 0.000ns 0.000ns 2.700ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" "" { Report "C:/altera/quartus50/lcd1602/db/lcd1602_cmp.qrpt" Compiler "lcd1602" "UNKNOWN" "V1" "C:/altera/quartus50/lcd1602/db/lcd1602.quartus_db" { Floorplan "C:/altera/quartus50/lcd1602/" "" "1.600 ns" { LCD_Data[1]~reg0 LCD_Data[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { LCD_Data[1]~reg0 LCD_Data[1] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}