capacityrammodel.vhd

来自「Capacity RAM Model的VHDL的例子。最佳的资源优化版。」· VHDL 代码 · 共 51 行

-- Function: 64k x 16 SRAM with separate I/O. OE 
--   WE latches data on rising edge
library ieee;  
library vfp;
  use ieee.std_logic_1164.all;
  use vfp.generic_functions.all;
entity sram_64k_16 is
generic (
  -- more to do with attribute'ing
  architecture_DNH_filename : string := "????????
);              
port (
  address  : in  std_ulogic_vector(15 downto 0);
  CS       : in  std_ulogic;
  WE       : in  std_ulogic;
  OE       : in  std_ulogic;
  data_in  : in  std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
begin
  -- data bus width must be integer power of 2 bits, < 64
  assert is_factor_of_32(data_in'length)
    report "Width of data bus must be 1, 2, 4, 8, 16 or 32 bits."
    severity warning;
end sram_64k_16;
-- Architectures:
--   12.02.96 original      PASSED SIMULATION
library memory;
architecture original of sram_64k_16 is
  use memory.sram_core_GENERIC_cmpt.all;
  constant address_width : integer := 16;
  constant data_width : integer := 16;
  
  attribute dnh_file_name : string(1 to 12);
  attribute dnh_file_name of sram_64k_16 : entity is architecture_DNH_filename; 
begin
  G1: sram_core_GENERIC 
    generic map (
      address_width => address_width,
      data_width => data_width
    )
    port map (
      address => address, 
      CS => CS, 
      WE => WE, 
      OE => OE, 
      data_in => data_in, 
      data_out => data_out
    );
  
end original;