fib.lst

FPGA RSIC CPU设计文档和源码是EDA中对CPU设计非常好用的程序

# generated by gr rev.1 on Fri Mar 09 21:40:11 2001

addr code  disassembly       source
---- ----  -----------       ------
                             # file sim-gr0.s
                             ; sim.s -- Simple simulator startup code
                             ; Copyright (C) 2000, Gray Research LLC.  All rights reserved.
                             ; Usage subject to XSOC License Agreement.  See the LICENSE file.
                             
                             global _main
                             
                             reti:
0000 0000  jal  r0,0(r0)     	jal r0,0(r0)
                             
                             intr:
0002 1EEE  addi sp,sp,-2     	lea sp,-2(sp)
0004 60E0  sw   r0,0(sp)     	sw r0,0(sp)
0006 2003  xor  r0,r0        	xor r0,r0
                             
0008 8800  imm  8000             sb r0,0x8007 ; re-enable timer int
000A 7007  sb   r0,7(r0)     
                             
000C 40E0  lw   r0,0(sp)     	lw r0,0(sp)
000E 1EE2  addi sp,sp,2      	lea sp,2(sp)
0010 90F8  br   0004         	br reti
                             
0012 0000  jal  r0,0(r0)     align 32
0014 0000  jal  r0,0(r0)     
0016 0000  jal  r0,0(r0)     
0018 0000  jal  r0,0(r0)     
001A 0000  jal  r0,0(r0)     
001C 0000  jal  r0,0(r0)     
001E 0000  jal  r0,0(r0)     
                             reset:
0020 2003  xor  r0,r0        	xor r0,r0
0022 803F  imm  03F0         	lea sp,0x3FE
0024 1E0E  addi sp,r0,-2     
0026 8002  imm  0020         	call _main
0028 0F0E  jal  r15,14(r0)   
002A 8002  imm  0020         	j reset
002C 0100  jal  r1,0(r0)     
                             # file fib.s
                             ; generated by lcc-gr0000 rev.3 on Fri Mar 09 21:35:21 2001
                             
                             global _main
                             align 2
                             _main:
002E 1EEA  addi sp,sp,-6     addi sp,sp,-6
0030 6BE0  sw   r11,0(sp)    sw r11,0(sp)
0032 6CE2  sw   r12,2(sp)    sw r12,2(sp)
0034 6DE4  sw   r13,4(sp)    sw r13,4(sp)
0036 1B01  addi r11,r0,1     lea r11,1
0038 1D01  addi r13,r0,1     lea r13,1
003A 1C01  addi r12,r0,1     lea r12,1
003C 9005  br   004A         br L4
                             L3:
003E 1CB0  addi r12,r11,0    mov r12,r11
0040 2CD0  add  r12,r13      add r12,r13
0042 1BD0  addi r11,r13,0    mov r11,r13
0044 1DC0  addi r13,r12,0    mov r13,r12
                             L4:
0046 8271  imm  2710         rcmpi r12,10000
0048 3C60  rcmpi r12,0       
004A 99FA  bge  0042         bge L3
004C 12B0  addi r2,r11,0     mov r2,r11
                             L2:
004E 4BE0  lw   r11,0(sp)    lw r11,0(sp)
0050 4CE2  lw   r12,2(sp)    lw r12,2(sp)
0052 4DE4  lw   r13,4(sp)    lw r13,4(sp)
0054 1EE6  addi sp,sp,6      addi sp,sp,6
0056 01F2  jal  r1,2(r15)    ret
                             
                             # file end.s
                             ; end.s -- Simple simulator epilog code
                             ; Copyright (C) 2000, Gray Research LLC.  All rights reserved.
                             ; Usage subject to XSOC License Agreement.  See the LICENSE file.
                             
                             end: