simple ram model.vhd

来自「一个SIMPLE RAM ACCESS的VHDL很经典的例子」· VHDL 代码 · 共 29 行

-- Architectures:
-- Behaviour
--Simple RAM Model by s0g0

library IEEE;
use IEEE.std_logic_1164.all;
use vfp.generic_conversions.all;
entity RamChip is
  port (Address: in Std_logic_vector(3 downto 0);
        Data: inout Std_logic_vector(7 downto 0);
        CS, WE, OE: in Std_logic);
end;
architecture Behaviour of RamChip is
begin
  process(Address, CS, WE, OE)
    subtype Byte is Std_logic_vector(7 downto 0);
    type Mem is array (0 to 15) of Byte;
    variable Memory: Mem := (others => Byte'(others=>'U'));
  begin
    Data <= (others => 'Z');
    if CS  = '0' then
      if OE = '0' then -- Read operation
        Data <= Memory(To_Integer(Address));
      elsif WE = '0' then -- Write operation
        Memory(To_Integer(Address)) := Data;
      end if;
    end if;
  end process;
end;