lab4_a1.lst

Digital Clock in Assembly 我的一个大学满分VHDL作品

A51 MACRO ASSEMBLER  LAB4_A1                                                              12/27/2005 19:42:04 PAGE     1


MACRO ASSEMBLER A51 V7.10
OBJECT MODULE PLACED IN LAB4_A1.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE LAB4_A1.a51 SET(SMALL) DEBUG EP

LOC  OBJ            LINE     SOURCE

                       1     ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                             ~~/
                       2     ;        
                       3     ;       Course               :  EE2800 Aspect Of Electrical Engineering (PART B)
                       4     ;
                       5     ;       Lab4                 :  Digital Clock in Assembly
                       6     ;
                       7     ;       Group number         : LAB4_A1
                       8     ;
                       9     ;       Group Member         :  NAME: PANG YANG           STUDENT ID : 3051364 
                      10     ;                            :  NAME: YU TAO              STUDENT ID : 3052730
                      11     ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                             ~/          
                      12     
                      13     
                      14     
0000                  15                  ORG  0000H    ;Begin program at 0000H
0000 020100           16                  LJMP INIT     
0003                  17                  ORG  0003H    ;Begin program at 0003H
0003 020144           18                  LJMP INT0_ISR  ;call ISR
0013                  19                  ORG  0013H    ;Begin program at 0013H
0013 020149           20                  LJMP INT1_ISR  ;call ISR
                      21     
                      22     
0016 7800             23     MAIN:        MOV  R0, #00H  ;clear R0
0018 7900             24                  MOV  R1, #00H  ;clear R1
001A 7A00             25                  MOV  R2, #00H  ;clear R2
001C 7B00             26                  MOV  R3, #00H  ;clear R3
                      27     
0100                  28                  ORG 0100H      ;starting address
0100 75A885           29     INIT:        MOV  IE,#085H  ;enbale interrupt 
0103 D288             30                  SETB TCON.0    ; edge sensitive
0105 D28A             31                  SETB TCON.2    ; edge sensitive
                      32     
                      33     
0107 8880             34     TMRUN:       MOV  P0, R0   ; copy content from R0 to P0
0109 8990             35                  MOV  P1, R1   ; copy content from R1 to P1
010B 8AA0             36                  MOV  P2, R2   ; copy content from R2 to P2
010D 8BB0             37                  MOV  P3, R3   ; copy content from R3 to P3
                      38     
010F 312C             39                 CALL DELAY1S   ; call delay1s
                      40     
                      41                
0111 08               42                  INC  R0              ; increase R0
0112 B80AF2           43                  CJNE R0, #0AH, TMRUN ; compare with 0AH, if not equal jump to TMRUN
0115 7800             44                  MOV  R0, #00H        ; clear R0
                      45     
                      46                
0117 09               47                  INC  R1              ; increase R1
0118 B906EC           48                  CJNE R1, #06H, TMRUN ;compare with 06H, if not equal jump to TMRUN
011B 7900             49                  MOV  R1, #00H        ; clear R1
                      50      
011D 0A               51                  INC  R2              ; increase R2
011E BA0AE6           52                  CJNE R2, #0AH, TMRUN ;compare with 06H, if not equal jump to TMRUN
0121 7A00             53                  MOV  R2, #00H       ; clear R2
                      54     
                      55                  
0123 0B               56                  INC  R3             ; increase R3
A51 MACRO ASSEMBLER  LAB4_A1                                                              12/27/2005 19:42:04 PAGE     2

0124 BB06E0           57                  CJNE R3, #06H, TMRUN ;compare with 06H, if not equal jump to TMRUN
0127 7B00             58                  MOV  R3, #00H       ; clear R3
                      59     
0129 020107           60                  LJMP  TMRUN
                      61     
                      62     
012C 7CFF             63     DELAY1S:     MOV  R4, #255       ; delay 1 seconds
012E 7D07             64     LOOP1:       MOV  R5, #7         ; time simultion.....
0130 00               65     LOOP2:       NOP  
0131 00               66     LOOP3:       NOP
0132 00               67                  NOP
0133 00               68                  NOP
0134 00               69                  NOP
0135 00               70                  NOP
0136 00               71                  NOP
0137 00               72                  NOP
0138 00               73                  NOP
0139 00               74                  NOP
013A 00               75                  NOP
013B 00               76                  NOP
013C 00               77                  NOP
013D DEF2             78                 DJNZ  R6, LOOP3 ; Decrement desitination by one, jump to loop3 if result not 0
013F DDEF             79                 DJNZ  R5, LOOP2
0141 DCEB             80                 DJNZ  R4, LOOP1
0143 22               81                 RET             
                      82     
                      83     
0144 7900             84     INT0_ISR:    MOV R1,#00H      ; clear R1 (seconds)
0146 7800             85                  MOV R0,#00H      ; clear R0 (seconds)
0148 32               86                  RETI
                      87     
0149 7B00             88     INT1_ISR:    MOV R3,#00H      ; clear R0 (seconds)
014B 7A00             89                  MOV R2,#00H      ; clear R0 (seconds)
014D 32               90                  RETI
                      91     
                      92     END;
A51 MACRO ASSEMBLER  LAB4_A1                                                              12/27/2005 19:42:04 PAGE     3

SYMBOL TABLE LISTING
------ ----- -------


N A M E             T Y P E  V A L U E   ATTRIBUTES

DELAY1S. . . . . .  C ADDR   012CH   A   
IE . . . . . . . .  D ADDR   00A8H   A   
INIT . . . . . . .  C ADDR   0100H   A   
INT0_ISR . . . . .  C ADDR   0144H   A   
INT1_ISR . . . . .  C ADDR   0149H   A   
LOOP1. . . . . . .  C ADDR   012EH   A   
LOOP2. . . . . . .  C ADDR   0130H   A   
LOOP3. . . . . . .  C ADDR   0131H   A   
MAIN . . . . . . .  C ADDR   0016H   A   
P0 . . . . . . . .  D ADDR   0080H   A   
P1 . . . . . . . .  D ADDR   0090H   A   
P2 . . . . . . . .  D ADDR   00A0H   A   
P3 . . . . . . . .  D ADDR   00B0H   A   
TCON . . . . . . .  D ADDR   0088H   A   
TMRUN. . . . . . .  C ADDR   0107H   A   


REGISTER BANK(S) USED: 0 


ASSEMBLY COMPLETE.  0 WARNING(S), 0 ERROR(S)