📄 pipeline_add_64.v
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module pipeline_add_64(cout,sum,ina,inb,cin,clk);
//input or output defination
input[63:0] ina;
input[63:0] inb;
input cin;
input clk;
output[63:0] sum;
output cout;
reg[63:0] tempa; //input reg
reg[63:0] tempb;
reg[63:0] sum; //output reg
reg[15:0] firsts; //first step sum reg
reg[15:0] thirda;
reg[15:0] thirdb; //third step data reg
reg[31:0] seconda; //second step data reg
reg[31:0] secondb;
reg[31:0] seconds; //second step sum reg
reg[47:0] firsta; //first step data reg
reg[47:0] firstb;
reg[47:0] thirds; //third step sum reg
reg tempci; //reg for cin
reg firstco; //reg for cout in first step
reg secondco; //reg for cout in second step
reg thirdco; //reg for cout in third step
reg cout; //cout output reg
always@(posedge clk)
begin
tempa<=ina;
tempb<=inb;
tempci<=cin;
end
always@(posedge clk)
begin
{firstco,firsts}<=tempa[15:0]+tempb[15:0]+tempci;
firsta<=tempa[63:16];
firstb<=tempb[63:16];
end
always@(posedge clk)
begin
{secondco,seconds}<={firsta[15:0]+firstb[15:0]+firstco,firsts};
seconda<=firsta[47:16];
secondb<=firstb[47:16];
end
always@(posedge clk)
begin
{thirdco,thirds}<={seconda[15:0]+secondb[15:0]+secondco,seconds};
thirda<=seconda[31:16];
thirdb<=secondb[31:16];
end
always@(posedge clk)
begin
{cout,sum}<={thirda[15:0]+thirdb[15:0]+thirdco,thirds};
end
endmodule
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