core_1c6.tan.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "ITDB_TSU_RESULT" "RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg P2\[7\] CLK_40 11.045 ns memory " "Info: tsu for memory \"RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg\" (data pin = \"P2\[7\]\", clock pin = \"CLK_40\") is 11.045 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.892 ns + Longest pin memory " "Info: + Longest pin to memory delay is 13.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns P2\[7\] 1 CLK PIN_228 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 8; CLK Node = 'P2\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P2[7] } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.039 ns) + CELL(0.590 ns) 9.104 ns Adr4_16:inst45\|CSout\[7\]~68 2 COMB LC_X19_Y14_N9 4 " "Info: 2: + IC(7.039 ns) + CELL(0.590 ns) = 9.104 ns; Loc. = LC_X19_Y14_N9; Fanout = 4; COMB Node = 'Adr4_16:inst45\|CSout\[7\]~68'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.629 ns" { P2[7] Adr4_16:inst45|CSout[7]~68 } "NODE_NAME" } "" } } { "Adr4_16.v" "" { Text "D:/Test_Phase/cexiang1/Adr4_16.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.969 ns) + CELL(0.442 ns) 11.515 ns inst36 3 COMB LC_X21_Y14_N9 2 " "Info: 3: + IC(1.969 ns) + CELL(0.442 ns) = 11.515 ns; Loc. = LC_X21_Y14_N9; Fanout = 2; COMB Node = 'inst36'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.411 ns" { Adr4_16:inst45|CSout[7]~68 inst36 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1200 -16 48 1248 "inst36" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.973 ns) + CELL(0.404 ns) 13.892 ns RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg 4 MEM M4K_X17_Y13 4 " "Info: 4: + IC(1.973 ns) + CELL(0.404 ns) = 13.892 ns; Loc. = M4K_X17_Y13; Fanout = 4; MEM Node = 'RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.377 ns" { inst36 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 265 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.911 ns ( 20.95 % ) " "Info: Total cell delay = 2.911 ns ( 20.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.981 ns ( 79.05 % ) " "Info: Total interconnect delay = 10.981 ns ( 79.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "13.892 ns" { P2[7] Adr4_16:inst45|CSout[7]~68 inst36 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.892 ns" { P2[7] P2[7]~out0 Adr4_16:inst45|CSout[7]~68 inst36 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } { 0.000ns 0.000ns 7.039ns 1.969ns 1.973ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 265 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40 destination 2.940 ns - Shortest memory " "Info: - Shortest clock path from clock \"CLK_40\" to destination memory is 2.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_40 1 CLK PIN_28 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 157; CLK Node = 'CLK_40'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { CLK_40 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.689 ns) 2.940 ns RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg 2 MEM M4K_X17_Y13 4 " "Info: 2: + IC(0.782 ns) + CELL(0.689 ns) = 2.940 ns; Loc. = M4K_X17_Y13; Fanout = 4; MEM Node = 'RAM_1K:inst17\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a7~portb_re_reg'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.471 ns" { CLK_40 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 265 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 73.40 % ) " "Info: Total cell delay = 2.158 ns ( 73.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.60 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.940 ns" { CLK_40 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.940 ns" { CLK_40 CLK_40~out0 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.689ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "13.892 ns" { P2[7] Adr4_16:inst45|CSout[7]~68 inst36 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.892 ns" { P2[7] P2[7]~out0 Adr4_16:inst45|CSout[7]~68 inst36 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } { 0.000ns 0.000ns 7.039ns 1.969ns 1.973ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.404ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.940 ns" { CLK_40 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.940 ns" { CLK_40 CLK_40~out0 RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a7~portb_re_reg } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.689ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_40 out0800\[2\] select_q:inst19\|out_q\[2\] 24.136 ns register " "Info: tco from clock \"CLK_40\" to destination pin \"out0800\[2\]\" through register \"select_q:inst19\|out_q\[2\]\" is 24.136 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40 source 17.313 ns + Longest register " "Info: + Longest clock path from clock \"CLK_40\" to source register is 17.313 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_40 1 CLK PIN_28 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 157; CLK Node = 'CLK_40'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { CLK_40 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fp_2:inst32\|Cout 2 REG LC_X15_Y10_N2 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X15_Y10_N2; Fanout = 2; REG Node = 'fp_2:inst32\|Cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.680 ns" { CLK_40 fp_2:inst32|Cout } "NODE_NAME" } "" } } { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 4.651 ns fp_2:inst18\|Cout 3 REG LC_X15_Y10_N4 30 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 4.651 ns; Loc. = LC_X15_Y10_N4; Fanout = 30; REG Node = 'fp_2:inst18\|Cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.502 ns" { fp_2:inst32|Cout fp_2:inst18|Cout } "NODE_NAME" } "" } } { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.263 ns) + CELL(0.935 ns) 9.849 ns fp_2:inst22\|Cout 4 REG LC_X26_Y10_N2 2 " "Info: 4: + IC(4.263 ns) + CELL(0.935 ns) = 9.849 ns; Loc. = LC_X26_Y10_N2; Fanout = 2; REG Node = 'fp_2:inst22\|Cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.