core_1c6.tan.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "ALE register register ScanKey:inst15\|Count\[0\] ScanKey:inst15\|KR_temp\[5\] 275.03 MHz Internal " "Info: Clock \"ALE\" Internal fmax is restricted to 275.03 MHz between source register \"ScanKey:inst15\|Count\[0\]\" and destination register \"ScanKey:inst15\|KR_temp\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.232 ns + Longest register register " "Info: + Longest register to register delay is 3.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ScanKey:inst15\|Count\[0\] 1 REG LC_X28_Y1_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y1_N1; Fanout = 7; REG Node = 'ScanKey:inst15\|Count\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ScanKey:inst15|Count[0] } "NODE_NAME" } "" } } { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.590 ns) 1.191 ns rtl~1 2 COMB LC_X28_Y1_N6 12 " "Info: 2: + IC(0.601 ns) + CELL(0.590 ns) = 1.191 ns; Loc. = LC_X28_Y1_N6; Fanout = 12; COMB Node = 'rtl~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.191 ns" { ScanKey:inst15|Count[0] rtl~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.174 ns) + CELL(0.867 ns) 3.232 ns ScanKey:inst15\|KR_temp\[5\] 3 REG LC_X29_Y1_N2 1 " "Info: 3: + IC(1.174 ns) + CELL(0.867 ns) = 3.232 ns; Loc. = LC_X29_Y1_N2; Fanout = 1; REG Node = 'ScanKey:inst15\|KR_temp\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.041 ns" { rtl~1 ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 45.08 % ) " "Info: Total cell delay = 1.457 ns ( 45.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.775 ns ( 54.92 % ) " "Info: Total interconnect delay = 1.775 ns ( 54.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "3.232 ns" { ScanKey:inst15|Count[0] rtl~1 ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.232 ns" { ScanKey:inst15|Count[0] rtl~1 ScanKey:inst15|KR_temp[5] } { 0.000ns 0.601ns 1.174ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 7.044 ns + Shortest register " "Info: + Shortest clock path from clock \"ALE\" to destination register is 7.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns ALE 1 CLK PIN_226 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_226; Fanout = 31; CLK Node = 'ALE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ALE } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 -32 136 256 "ALE" "" } { 256 184 256 272 "ALE" "" } { 16 208 248 32 "ALE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.858 ns) + CELL(0.711 ns) 7.044 ns ScanKey:inst15\|KR_temp\[5\] 2 REG LC_X29_Y1_N2 1 " "Info: 2: + IC(4.858 ns) + CELL(0.711 ns) = 7.044 ns; Loc. = LC_X29_Y1_N2; Fanout = 1; REG Node = 'ScanKey:inst15\|KR_temp\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "5.569 ns" { ALE ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 31.03 % ) " "Info: Total cell delay = 2.186 ns ( 31.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.858 ns ( 68.97 % ) " "Info: Total interconnect delay = 4.858 ns ( 68.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|KR_temp[5] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE source 7.044 ns - Longest register " "Info: - Longest clock path from clock \"ALE\" to source register is 7.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns ALE 1 CLK PIN_226 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_226; Fanout = 31; CLK Node = 'ALE'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ALE } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 -32 136 256 "ALE" "" } { 256 184 256 272 "ALE" "" } { 16 208 248 32 "ALE" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.858 ns) + CELL(0.711 ns) 7.044 ns ScanKey:inst15\|Count\[0\] 2 REG LC_X28_Y1_N1 7 " "Info: 2: + IC(4.858 ns) + CELL(0.711 ns) = 7.044 ns; Loc. = LC_X28_Y1_N1; Fanout = 7; REG Node = 'ScanKey:inst15\|Count\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "5.569 ns" { ALE ScanKey:inst15|Count[0] } "NODE_NAME" } "" } } { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 31.03 % ) " "Info: Total cell delay = 2.186 ns ( 31.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.858 ns ( 68.97 % ) " "Info: Total interconnect delay = 4.858 ns ( 68.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|Count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|Count[0] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|KR_temp[5] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|Count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|Count[0] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "3.232 ns" { ScanKey:inst15|Count[0] rtl~1 ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.232 ns" { ScanKey:inst15|Count[0] rtl~1 ScanKey:inst15|KR_temp[5] } { 0.000ns 0.601ns 1.174ns } { 0.000ns 0.590ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|KR_temp[5] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "7.044 ns" { ALE ScanKey:inst15|Count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.044 ns" { ALE ALE~out0 ScanKey:inst15|Count[0] } { 0.000ns 0.000ns 4.858ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ScanKey:inst15|KR_temp[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { ScanKey:inst15|KR_temp[5] } {  } {  } } } { "scankey.v" "" { Text "D:/Test_Phase/cexiang1/scankey.v" 61 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_40 register add18:inst47\|SUM\[18\] memory RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3 88.95 MHz 11.242 ns Internal " "Info: Clock \"CLK_40\" has Internal fmax of 88.95 MHz between source register \"add18:inst47\|SUM\[18\]\" and destination memory \"RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3\" (period= 11.242 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.271 ns + Longest register memory " "Info: + Longest register to memory delay is 4.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add18:inst47\|SUM\[18\] 1 REG LC_X19_Y12_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y12_N9; Fanout = 6; REG Node = 'add18:inst47\|SUM\[18\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { add18:inst47|SUM[18] } "NODE_NAME" } "" } } { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.114 ns) 1.436 ns inst37 2 COMB LC_X20_Y13_N5 56 " "Info: 2: + IC(1.322 ns) + CELL(0.114 ns) = 1.436 ns; Loc. = LC_X20_Y13_N5; Fanout = 56; COMB Node = 'inst37'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.436 ns" { add18:inst47|SUM[18] inst37 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 960 -24 40 1008 "inst37" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.870 ns) + CELL(0.965 ns) 4.271 ns RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3 3 MEM M4K_X17_Y15 1 " "Info: 3: + IC(1.870 ns) + CELL(0.965 ns) = 4.271 ns; Loc. = M4K_X17_Y15; Fanout = 1; MEM Node = 'RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.835 ns" { inst37 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 234 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.079 ns ( 25.26 % ) " "Info: Total cell delay = 1.079 ns ( 25.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.192 ns ( 74.74 % ) " "Info: Total interconnect delay = 3.192 ns ( 74.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "4.271 ns" { add18:inst47|SUM[18] inst37 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.271 ns" { add18:inst47|SUM[18] inst37 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } { 0.000ns 1.322ns 1.870ns } { 0.000ns 0.114ns 0.965ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.654 ns - Smallest " "Info: - Smallest clock skew is -6.654 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40 destination 2.973 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK_40\" to destination memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_40 1 CLK PIN_28 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 157; CLK Node = 'CLK_40'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { CLK_40 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3 2 MEM M4K_X17_Y15 1 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y15; Fanout = 1; MEM Node = 'RAM_1K:inst5\|altsyncram:altsyncram_component\|altsyncram_aqb1:auto_generated\|ram_block1a6~porta_datain_reg3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.504 ns" { CLK_40 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 234 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 73.70 % ) " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.30 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.973 ns" { CLK_40 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.973 ns" { CLK_40 CLK_40~out0 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40 source 9.627 ns - Longest register " "Info: - Longest clock path from clock \"CLK_40\" to source register is 9.627 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_40 1 CLK PIN_28 157 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 157; CLK Node = 'CLK_40'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { CLK_40 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fp_2:inst32\|Cout 2 REG LC_X15_Y10_N2 2 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X15_Y10_N2; Fanout = 2; REG Node = 'fp_2:inst32\|Cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.680 ns" { CLK_40 fp_2:inst32|Cout } "NODE_NAME" } "" } } { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 4.651 ns fp_2:inst18\|Cout 3 REG LC_X15_Y10_N4 30 " "Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 4.651 ns; Loc. = LC_X15_Y10_N4; Fanout = 30; REG Node = 'fp_2:inst18\|Cout'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.502 ns" { fp_2:inst32|Cout fp_2:inst18|Cout } "NODE_NAME" } "" } } { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.265 ns) + CELL(0.711 ns) 9.627 ns add18:inst47\|SUM\[18\] 4 REG LC_X19_Y12_N9 6 " "Info: 4: + IC(4.265 ns) + CELL(0.711 ns) = 9.627 ns; Loc. = LC_X19_Y12_N9; Fanout = 6; REG Node = 'add18:inst47\|SUM\[18\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "4.976 ns" { fp_2:inst18|Cout add18:inst47|SUM[18] } "NODE_NAME" } "" } } { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 42.07 % ) " "Info: Total cell delay = 4.050 ns ( 42.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.577 ns ( 57.93 % ) " "Info: Total interconnect delay = 5.577 ns ( 57.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "9.627 ns" { CLK_40 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.627 ns" { CLK_40 CLK_40~out0 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } { 0.000ns 0.000ns 0.745ns 0.567ns 4.265ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.973 ns" { CLK_40 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.973 ns" { CLK_40 CLK_40~out0 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "9.627 ns" { CLK_40 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.627 ns" { CLK_40 CLK_40~out0 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } { 0.000ns 0.000ns 0.745ns 0.567ns 4.265ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "add18.v" "" { Text "D:/Test_Phase/cexiang1/add18.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_aqb1.tdf" "" { Text "D:/Test_Phase/cexiang1/db/altsyncram_aqb1.tdf" 234 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "4.271 ns" { add18:inst47|SUM[18] inst37 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.271 ns" { add18:inst47|SUM[18] inst37 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } { 0.000ns 1.322ns 1.870ns } { 0.000ns 0.114ns 0.965ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "2.973 ns" { CLK_40 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.973 ns" { CLK_40 CLK_40~out0 RAM_1K:inst5|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated|ram_block1a6~porta_datain_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "9.627 ns" { CLK_40 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.627 ns" { CLK_40 CLK_40~out0 fp_2:inst32|Cout fp_2:inst18|Cout add18:inst47|SUM[18] } { 0.000ns 0.000ns 0.745ns 0.567ns 4.265ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Fre17 register register ce_gao:inst12\|jud2 ce_gao:inst12\|jud3~reg0 275.03 MHz Internal " "Info: Clock \"Fre17\" Internal fmax is restricted to 275.03 MHz between source register \"ce_gao:inst12\|jud2\" and destination register \"ce_gao:inst12\|jud3~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.045 ns + Longest register register " "Info: + Longest register to register delay is 1.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ce_gao:inst12\|jud2 1 REG LC_X19_Y15_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y15_N9; Fanout = 2; REG Node = 'ce_gao:inst12\|jud2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.309 ns) 1.045 ns ce_gao:inst12\|jud3~reg0 2 REG LC_X20_Y15_N2 2 " "Info: 2: + IC(0.736 ns) + CELL(0.309 ns) = 1.045 ns; Loc. = LC_X20_Y15_N2; Fanout = 2; REG Node = 'ce_gao:inst12\|jud3~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.045 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 29.57 % ) " "Info: Total cell delay = 0.309 ns ( 29.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.736 ns ( 70.43 % ) " "Info: Total interconnect delay = 0.736 ns ( 70.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.045 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.045 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } { 0.000ns 0.736ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fre17 destination 10.734 ns + Shortest register " "Info: + Shortest clock path from clock \"Fre17\" to destination register is 10.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Fre17 1 CLK PIN_23 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 4; CLK Node = 'Fre17'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { Fre17 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1584 -616 -448 1600 "Fre17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.554 ns) + CELL(0.711 ns) 10.734 ns ce_gao:inst12\|jud3~reg0 2 REG LC_X20_Y15_N2 2 " "Info: 2: + IC(8.554 ns) + CELL(0.711 ns) = 10.734 ns; Loc. = LC_X20_Y15_N2; Fanout = 2; REG Node = 'ce_gao:inst12\|jud3~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "9.265 ns" { Fre17 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 20.31 % ) " "Info: Total cell delay = 2.180 ns ( 20.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.554 ns ( 79.69 % ) " "Info: Total interconnect delay = 8.554 ns ( 79.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud3~reg0 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fre17 source 10.734 ns - Longest register " "Info: - Longest clock path from clock \"Fre17\" to source register is 10.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Fre17 1 CLK PIN_23 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 4; CLK Node = 'Fre17'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { Fre17 } "NODE_NAME" } "" } } { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1584 -616 -448 1600 "Fre17" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.554 ns) + CELL(0.711 ns) 10.734 ns ce_gao:inst12\|jud2 2 REG LC_X19_Y15_N9 2 " "Info: 2: + IC(8.554 ns) + CELL(0.711 ns) = 10.734 ns; Loc. = LC_X19_Y15_N9; Fanout = 2; REG Node = 'ce_gao:inst12\|jud2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "9.265 ns" { Fre17 ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 20.31 % ) " "Info: Total cell delay = 2.180 ns ( 20.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.554 ns ( 79.69 % ) " "Info: Total interconnect delay = 8.554 ns ( 79.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud2 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud3~reg0 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud2 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 4 -1 0 } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.045 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.045 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } { 0.000ns 0.736ns } { 0.000ns 0.309ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud3~reg0 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "10.734 ns" { Fre17 ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.734 ns" { Fre17 Fre17~out0 ce_gao:inst12|jud2 } { 0.000ns 0.000ns 8.554ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { ce_gao:inst12|jud3~reg0 } {  } {  } } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}