core_1c6.tan.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[7\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[7\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[6\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[6\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[5\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[5\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[4\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[4\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[0\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[0\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[1\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[1\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[2\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[2\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "BUS_Connect:inst9\|Data_Temp\[3\] " "Warning: Node \"BUS_Connect:inst9\|Data_Temp\[3\]\" is a latch" {  } { { "bus_connect.v" "" { Text "D:/Test_Phase/cexiang1/bus_connect.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 -32 136 256 "ALE" "" } { 256 184 256 272 "ALE" "" } { 16 208 248 32 "ALE" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_40 " "Info: Assuming node \"CLK_40\" is an undefined clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_40" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Fre17 " "Info: Assuming node \"Fre17\" is an undefined clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1584 -616 -448 1600 "Fre17" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Fre17" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "P2\[7\] " "Info: Assuming node \"P2\[7\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "P2\[3\] " "Info: Assuming node \"P2\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "P2\[4\] " "Info: Assuming node \"P2\[4\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "P2\[5\] " "Info: Assuming node \"P2\[5\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "P2\[6\] " "Info: Assuming node \"P2\[6\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 344 -8 160 360 "P2\[7..0\]" "" } { 264 488 523 280 "P2\[1\]" "" } { 376 200 248 392 "P2\[7\]" "" } { 392 208 248 408 "P2\[6..3\]" "" } { 680 336 392 696 "P2\[6..0\]" "" } { 1632 40 112 1648 "P2\[1..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "rtl~195 " "Info: Detected gated clock \"rtl~195\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~195" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp_2:inst22\|Cout " "Info: Detected ripple clock \"fp_2:inst22\|Cout\" as buffer" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp_2:inst22\|Cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp_2:inst25\|Cout " "Info: Detected ripple clock \"fp_2:inst25\|Cout\" as buffer" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp_2:inst25\|Cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp_2:inst26\|Cout " "Info: Detected ripple clock \"fp_2:inst26\|Cout\" as buffer" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp_2:inst26\|Cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~194 " "Info: Detected gated clock \"rtl~194\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~194" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp_2:inst32\|Cout " "Info: Detected ripple clock \"fp_2:inst32\|Cout\" as buffer" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp_2:inst32\|Cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fp_2:inst18\|Cout " "Info: Detected ripple clock \"fp_2:inst18\|Cout\" as buffer" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "fp_2:inst18\|Cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "BUS_Connect:inst9\|Select~459 " "Info: Detected gated clock \"BUS_Connect:inst9\|Select~459\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "BUS_Connect:inst9\|Select~459" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}