📄 core_1c6.fit.qmsg
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "8 " "Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[7\] a permanently disabled " "Info: Pin P1\[7\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[7] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[6\] a permanently disabled " "Info: Pin P1\[6\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[6] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[5\] a permanently enabled " "Info: Pin P1\[5\] has a permanently enabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[5] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[4\] a permanently disabled " "Info: Pin P1\[4\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[4] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[3\] a permanently disabled " "Info: Pin P1\[3\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[3] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[2\] a permanently disabled " "Info: Pin P1\[2\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[1\] a permanently disabled " "Info: Pin P1\[1\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[1] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFSAC_FSAC_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "P1\[0\] a permanently disabled " "Info: Pin P1\[0\] has a permanently disabled output enable" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[0] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "17 " "Warning: Following 17 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FS GND " "Info: Pin FS has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 464 560 736 480 "FS" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FS" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { FS } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { FS } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "EA VCC " "Info: Pin EA has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 600 528 704 616 "EA" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "EA" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { EA } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { EA } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[7\] GND " "Info: Pin LED\[7\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[7] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[6\] GND " "Info: Pin LED\[6\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[6] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[5\] GND " "Info: Pin LED\[5\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[5] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[4\] GND " "Info: Pin LED\[4\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[4] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[3\] GND " "Info: Pin LED\[3\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[3] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[2\] GND " "Info: Pin LED\[2\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[1\] GND " "Info: Pin LED\[1\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[1] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LED\[0\] GND " "Info: Pin LED\[0\] has GND driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 376 576 752 392 "LED\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LED\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { LED[0] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { LED[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[7\] VCC " "Info: Pin P1\[7\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[7] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[6\] VCC " "Info: Pin P1\[6\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[6] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[4\] VCC " "Info: Pin P1\[4\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[4] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[3\] VCC " "Info: Pin P1\[3\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[3] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[2\] VCC " "Info: Pin P1\[2\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[1\] VCC " "Info: Pin P1\[1\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[1] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "P1\[0\] VCC " "Info: Pin P1\[0\] has VCC driving its datain port" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 816 -376 -200 832 "P1\[7..0\]" "" } { 1384 120 184 1400 "P1\[0\]" "" } { 864 632 720 880 "P1\[3\]" "" } { 1760 864 928 1776 "P1\[5\]" "" } { 976 840 888 992 "P1\[6\]" "" } { 1008 536 576 1024 "P1\[3\]" "" } { 1408 456 512 1424 "P1\[0\]" "" } { 1144 840 875 1160 "P1\[5\]" "" } { 1192 608 688 1208 "P1\[5\]" "" } { 976 -72 -24 992 "P1\[5\]" "" } { 1176 -104 -16 1192 "P1\[5\]" "" } { 1280 472 520 1296 "P1\[4\]" "" } { 1584 40 112 1600 "P1\[2\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P1\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P1[0] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "rtl~2 " "Info: Following pins have the same output enable: rtl~2" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KC\[2\] LVTTL " "Info: Type bidirectional pin KC\[2\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 16 424 600 32 "KC\[2..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KC\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KC[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KC[2] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KC\[1\] LVTTL " "Info: Type bidirectional pin KC\[1\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 16 424 600 32 "KC\[2..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KC\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KC[1] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KC[1] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KC\[0\] LVTTL " "Info: Type bidirectional pin KC\[0\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 16 424 600 32 "KC\[2..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KC\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KC[0] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KC[0] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "rtl~1 " "Info: Following pins have the same output enable: rtl~1" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[5\] LVTTL " "Info: Type bidirectional pin KR\[5\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[5] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[5] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[4\] LVTTL " "Info: Type bidirectional pin KR\[4\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[4] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[4] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[3\] LVTTL " "Info: Type bidirectional pin KR\[3\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[3] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[3] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[2\] LVTTL " "Info: Type bidirectional pin KR\[2\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[2] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[1\] LVTTL " "Info: Type bidirectional pin KR\[1\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[1] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[1] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional KR\[0\] LVTTL " "Info: Type bidirectional pin KR\[0\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 40 504 680 56 "KR\[5..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "KR\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { KR[0] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { KR[0] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "BUS_Connect:inst9\|Dout~0 " "Info: Following pins have the same output enable: BUS_Connect:inst9\|Dout~0" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[7\] LVTTL " "Info: Type bidirectional pin P0\[7\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[7] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[7] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[6\] LVTTL " "Info: Type bidirectional pin P0\[6\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[6] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[6] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[5\] LVTTL " "Info: Type bidirectional pin P0\[5\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[5] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[5] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[4\] LVTTL " "Info: Type bidirectional pin P0\[4\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[4] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[4] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[3\] LVTTL " "Info: Type bidirectional pin P0\[3\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[3] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[3] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[2\] LVTTL " "Info: Type bidirectional pin P0\[2\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { P0[2] } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { P0[2] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[1\] LVTTL " "Info: Type bidirectional pin P0\[1\] uses the LVTTL I/O standard" { } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 304 -24 152 320 "P0\[7..0\]" "" } { 272 184 256 288 "P0\[7..0\]" "" } { 504 312 368 520 "P0\[7..0\]" "" } { 184 176 232 200 "P0\[7..0\]" "" } { 1128 656 694 1144 "P0\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "P0\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db⌨️ 快捷键说明
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