core_1c6.fit.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.137 ns register register " "Info: Estimated most critical path is register to register delay of 1.137 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ce_gao:inst12\|jud2 1 REG LAB_X19_Y15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y15; Fanout = 2; REG Node = 'ce_gao:inst12\|jud2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ce_gao:inst12|jud2 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.607 ns) 1.137 ns ce_gao:inst12\|jud3~reg0 2 REG LAB_X20_Y15 2 " "Info: 2: + IC(0.530 ns) + CELL(0.607 ns) = 1.137 ns; Loc. = LAB_X20_Y15; Fanout = 2; REG Node = 'ce_gao:inst12\|jud3~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.137 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } } { "ce_gao.v" "" { Text "D:/Test_Phase/cexiang1/ce_gao.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 53.39 % ) " "Info: Total cell delay = 0.607 ns ( 53.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.530 ns ( 46.61 % ) " "Info: Total interconnect delay = 0.530 ns ( 46.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "1.137 ns" { ce_gao:inst12|jud2 ce_gao:inst12|jud3~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 8 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 8%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}