core_1c6.fit.qmsg

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK_40 Global clock in PIN 28 " "Info: Automatically promoted signal \"CLK_40\" to use Global clock in PIN 28" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1120 -248 -80 1136 "CLK_40" "" } { 1048 96 176 1064 "Clk_40" "" } { 1248 64 136 1264 "Clk_40" "" } { 1240 -544 -488 1256 "CLK_40" "" } { 1568 40 112 1584 "CLK_40" "" } { 1808 -416 -352 1824 "CLK_40" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fp_2:inst18\|Cout Global clock " "Info: Automatically promoted some destinations of signal \"fp_2:inst18\|Cout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fp_2:inst18\|Cout " "Info: Destination \"fp_2:inst18\|Cout\" may be non-global or may not use global clock" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "inst37 " "Info: Destination \"inst37\" may be non-global or may not use global clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 960 -24 40 1008 "inst37" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ALE Global clock " "Info: Automatically promoted signal \"ALE\" to use Global clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 -32 136 256 "ALE" "" } { 256 184 256 272 "ALE" "" } { 16 208 248 32 "ALE" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "ALE " "Info: Pin \"ALE\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 240 -32 136 256 "ALE" "" } { 256 184 256 272 "ALE" "" } { 16 208 248 32 "ALE" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { ALE } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { ALE } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fp_2:inst26\|Cout Global clock " "Info: Automatically promoted some destinations of signal \"fp_2:inst26\|Cout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fp_2:inst26\|Cout " "Info: Destination \"fp_2:inst26\|Cout\" may be non-global or may not use global clock" {  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "fp_2.v" "" { Text "D:/Test_Phase/cexiang1/fp_2.v" 13 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~195 Global clock " "Info: Automatically promoted signal \"rtl~195\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~195" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { rtl~195 } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { rtl~195 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Fre17 Global clock " "Info: Automatically promoted some destinations of signal \"Fre17\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "out7 " "Info: Destination \"out7\" may be non-global or may not use global clock" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1792 840 1016 1808 "out7" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1584 -616 -448 1600 "Fre17" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "Fre17 " "Info: Pin \"Fre17\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "core_1c6.bdf" "" { Schematic "D:/Test_Phase/cexiang1/core_1c6.bdf" { { 1584 -616 -448 1600 "Fre17" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Fre17" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "core_1c6" "UNKNOWN" "V1" "D:/Test_Phase/cexiang1/db/core_1c6.quartus_db" { Floorplan "D:/Test_Phase/cexiang1/" "" "" { Fre17 } "NODE_NAME" } "" } } { "D:/Test_Phase/cexiang1/core_1c6.fld" "" { Floorplan "D:/Test_Phase/cexiang1/core_1c6.fld" "" "" { Fre17 } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}