core_1c6.hier_info

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0


|core_1c6|BUS_Connect:inst9
Din0[0] => Select~7.IN10
Din0[1] => Select~6.IN10
Din0[2] => Select~5.IN10
Din0[3] => Select~4.IN10
Din0[4] => Select~3.IN10
Din0[5] => Select~2.IN10
Din0[6] => Select~1.IN10
Din0[7] => Select~0.IN10
Din1[0] => Select~7.IN11
Din1[1] => Select~6.IN11
Din1[2] => Select~5.IN11
Din1[3] => Select~4.IN11
Din1[4] => Select~3.IN11
Din1[5] => Select~2.IN11
Din1[6] => Select~1.IN11
Din1[7] => Select~0.IN11
Din2[0] => Select~7.IN12
Din2[1] => Select~6.IN12
Din2[2] => Select~5.IN12
Din2[3] => Select~4.IN12
Din2[4] => Select~3.IN12
Din2[5] => Select~2.IN12
Din2[6] => Select~1.IN12
Din2[7] => Select~0.IN12
Din3[0] => Select~7.IN13
Din3[1] => Select~6.IN13
Din3[2] => Select~5.IN13
Din3[3] => Select~4.IN13
Din3[4] => Select~3.IN13
Din3[5] => Select~2.IN13
Din3[6] => Select~1.IN13
Din3[7] => Select~0.IN13
Din4[0] => Select~7.IN14
Din4[1] => Select~6.IN14
Din4[2] => Select~5.IN14
Din4[3] => Select~4.IN14
Din4[4] => Select~3.IN14
Din4[5] => Select~2.IN14
Din4[6] => Select~1.IN14
Din4[7] => Select~0.IN14
Din5[0] => Select~7.IN15
Din5[1] => Select~6.IN15
Din5[2] => Select~5.IN15
Din5[3] => Select~4.IN15
Din5[4] => Select~3.IN15
Din5[5] => Select~2.IN15
Din5[6] => Select~1.IN15
Din5[7] => Select~0.IN15
Din6[0] => Select~7.IN16
Din6[1] => Select~6.IN16
Din6[2] => Select~5.IN16
Din6[3] => Select~4.IN16
Din6[4] => Select~3.IN16
Din6[5] => Select~2.IN16
Din6[6] => Select~1.IN16
Din6[7] => Select~0.IN16
Din7[0] => Select~7.IN17
Din7[1] => Select~6.IN17
Din7[2] => Select~5.IN17
Din7[3] => Select~4.IN17
Din7[4] => Select~3.IN17
Din7[5] => Select~2.IN17
Din7[6] => Select~1.IN17
Din7[7] => Select~0.IN17
Dout[0] <= Dout~8.DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout~7.DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout~6.DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout~5.DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout~4.DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout~3.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout~2.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout~1.DB_MAX_OUTPUT_PORT_TYPE
CS0 => Equal~0.IN15
CS0 => Decoder~0.IN7
CS1 => Equal~0.IN14
CS1 => Decoder~0.IN6
CS2 => Equal~0.IN13
CS2 => Decoder~0.IN5
CS3 => Equal~0.IN12
CS3 => Decoder~0.IN4
CS4 => Equal~0.IN11
CS4 => Decoder~0.IN3
CS5 => Equal~0.IN10
CS5 => Decoder~0.IN2
CS6 => Equal~0.IN9
CS6 => Decoder~0.IN1
CS7 => Equal~0.IN8
CS7 => Decoder~0.IN0
RD => Dout~0.IN1


|core_1c6|ce_gao:inst12
game => jud2~reg0.CLK
game => jud3~reg0.CLK
fc => counter[22].CLK
fc => counter[21].CLK
fc => counter[20].CLK
fc => counter[19].CLK
fc => counter[18].CLK
fc => counter[17].CLK
fc => counter[16].CLK
fc => counter[15].CLK
fc => counter[14].CLK
fc => counter[13].CLK
fc => counter[12].CLK
fc => counter[11].CLK
fc => counter[10].CLK
fc => counter[9].CLK
fc => counter[8].CLK
fc => counter[7].CLK
fc => counter[6].CLK
fc => counter[5].CLK
fc => counter[4].CLK
fc => counter[3].CLK
fc => counter[2].CLK
fc => counter[1].CLK
fc => counter[0].CLK
fc => counter[23].CLK
CS => ~NO_FANOUT~
rest => jud2~reg0.DATAIN
rest => jud3~1.OUTPUTSELECT
rest => counter~24.OUTPUTSELECT
rest => counter~25.OUTPUTSELECT
rest => counter~26.OUTPUTSELECT
rest => counter~27.OUTPUTSELECT
rest => counter~28.OUTPUTSELECT
rest => counter~29.OUTPUTSELECT
rest => counter~30.OUTPUTSELECT
rest => counter~31.OUTPUTSELECT
rest => counter~32.OUTPUTSELECT
rest => counter~33.OUTPUTSELECT
rest => counter~34.OUTPUTSELECT
rest => counter~35.OUTPUTSELECT
rest => counter~36.OUTPUTSELECT
rest => counter~37.OUTPUTSELECT
rest => counter~38.OUTPUTSELECT
rest => counter~39.OUTPUTSELECT
rest => counter~40.OUTPUTSELECT
rest => counter~41.OUTPUTSELECT
rest => counter~42.OUTPUTSELECT
rest => counter~43.OUTPUTSELECT
rest => counter~44.OUTPUTSELECT
rest => counter~45.OUTPUTSELECT
rest => counter~46.OUTPUTSELECT
rest => counter~47.OUTPUTSELECT
data[0] <= always3~8.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= always3~7.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= always3~6.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= always3~5.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= always3~4.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= always3~3.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= always3~2.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= always3~1.DB_MAX_OUTPUT_PORT_TYPE
addr[0] => Decoder~0.IN1
addr[1] => Decoder~0.IN0
RD => ~NO_FANOUT~
jud1 => jud3~0.OUTPUTSELECT
jud2 <= jud2~reg0.DB_MAX_OUTPUT_PORT_TYPE
jud3 <= jud3~reg0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|div_1000:inst33
clk_in => count[8].CLK
clk_in => count[7].CLK
clk_in => count[6].CLK
clk_in => count[5].CLK
clk_in => count[4].CLK
clk_in => count[3].CLK
clk_in => count[2].CLK
clk_in => count[1].CLK
clk_in => count[0].CLK
clk_in => clk_temp~reg0.CLK
clk_in => count[9].CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk_temp <= clk_temp~reg0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|CONTER8:inst35
clk_in => data_out[8]~reg0.CLK
clk_in => data_out[7]~reg0.CLK
clk_in => data_out[6]~reg0.CLK
clk_in => data_out[5]~reg0.CLK
clk_in => data_out[4]~reg0.CLK
clk_in => data_out[3]~reg0.CLK
clk_in => data_out[2]~reg0.CLK
clk_in => data_out[1]~reg0.CLK
clk_in => data_out[0]~reg0.CLK
clk_in => data_out[9]~reg0.CLK
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rst => data_out~0.OUTPUTSELECT
rst => data_out~1.OUTPUTSELECT
rst => data_out~2.OUTPUTSELECT
rst => data_out~3.OUTPUTSELECT
rst => data_out~4.OUTPUTSELECT
rst => data_out~5.OUTPUTSELECT
rst => data_out~6.OUTPUTSELECT
rst => data_out~7.OUTPUTSELECT
rst => data_out~8.OUTPUTSELECT
rst => data_out~9.OUTPUTSELECT