core_1c6.hier_info

运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形.

address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0


|core_1c6|RAM_ADDR:inst13
IN1[0] => OUT[0].DATAIN
IN1[1] => OUT[1].DATAIN
IN1[2] => OUT[2].DATAIN
IN1[3] => OUT[3].DATAIN
IN1[4] => OUT[4].DATAIN
IN1[5] => OUT[5].DATAIN
IN1[6] => OUT[6].DATAIN
IN1[7] => OUT[7].DATAIN
IN2[0] => OUT[8].DATAIN
IN2[1] => OUT[9].DATAIN
IN2[2] => OUT[10].DATAIN
IN2[3] => OUT[11].DATAIN
IN2[4] => OUT[12].DATAIN
IN2[5] => OUT[13].DATAIN
IN2[6] => OUT[14].DATAIN
OUT[0] <= IN1[0].DB_MAX_OUTPUT_PORT_TYPE
OUT[1] <= IN1[1].DB_MAX_OUTPUT_PORT_TYPE
OUT[2] <= IN1[2].DB_MAX_OUTPUT_PORT_TYPE
OUT[3] <= IN1[3].DB_MAX_OUTPUT_PORT_TYPE
OUT[4] <= IN1[4].DB_MAX_OUTPUT_PORT_TYPE
OUT[5] <= IN1[5].DB_MAX_OUTPUT_PORT_TYPE
OUT[6] <= IN1[6].DB_MAX_OUTPUT_PORT_TYPE
OUT[7] <= IN1[7].DB_MAX_OUTPUT_PORT_TYPE
OUT[8] <= IN2[0].DB_MAX_OUTPUT_PORT_TYPE
OUT[9] <= IN2[1].DB_MAX_OUTPUT_PORT_TYPE
OUT[10] <= IN2[2].DB_MAX_OUTPUT_PORT_TYPE
OUT[11] <= IN2[3].DB_MAX_OUTPUT_PORT_TYPE
OUT[12] <= IN2[4].DB_MAX_OUTPUT_PORT_TYPE
OUT[13] <= IN2[5].DB_MAX_OUTPUT_PORT_TYPE
OUT[14] <= IN2[6].DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|ASIC74573:inst
Ale => Dout[6]~reg0.CLK
Ale => Dout[5]~reg0.CLK
Ale => Dout[4]~reg0.CLK
Ale => Dout[3]~reg0.CLK
Ale => Dout[2]~reg0.CLK
Ale => Dout[1]~reg0.CLK
Ale => Dout[0]~reg0.CLK
Ale => Dout[7]~reg0.CLK
Din[0] => Dout[0]~reg0.DATAIN
Din[1] => Dout[1]~reg0.DATAIN
Din[2] => Dout[2]~reg0.DATAIN
Din[3] => Dout[3]~reg0.DATAIN
Din[4] => Dout[4]~reg0.DATAIN
Din[5] => Dout[5]~reg0.DATAIN
Din[6] => Dout[6]~reg0.DATAIN
Din[7] => Dout[7]~reg0.DATAIN
Dout[0] <= Dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|core_1c6|RAM_1K:inst17
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~9.IN1
wraddress[1] => wraddress[1]~8.IN1
wraddress[2] => wraddress[2]~7.IN1
wraddress[3] => wraddress[3]~6.IN1
wraddress[4] => wraddress[4]~5.IN1
wraddress[5] => wraddress[5]~4.IN1
wraddress[6] => wraddress[6]~3.IN1
wraddress[7] => wraddress[7]~2.IN1
wraddress[8] => wraddress[8]~1.IN1
wraddress[9] => wraddress[9]~0.IN1
rdaddress[0] => rdaddress[0]~9.IN1
rdaddress[1] => rdaddress[1]~8.IN1
rdaddress[2] => rdaddress[2]~7.IN1
rdaddress[3] => rdaddress[3]~6.IN1
rdaddress[4] => rdaddress[4]~5.IN1
rdaddress[5] => rdaddress[5]~4.IN1
rdaddress[6] => rdaddress[6]~3.IN1
rdaddress[7] => rdaddress[7]~2.IN1
rdaddress[8] => rdaddress[8]~1.IN1
rdaddress[9] => rdaddress[9]~0.IN1
rden => rden~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|core_1c6|RAM_1K:inst17|altsyncram:altsyncram_component
wren_a => altsyncram_aqb1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => altsyncram_aqb1:auto_generated.rden_b
data_a[0] => altsyncram_aqb1:auto_generated.data_a[0]
data_a[1] => altsyncram_aqb1:auto_generated.data_a[1]
data_a[2] => altsyncram_aqb1:auto_generated.data_a[2]
data_a[3] => altsyncram_aqb1:auto_generated.data_a[3]
data_a[4] => altsyncram_aqb1:auto_generated.data_a[4]
data_a[5] => altsyncram_aqb1:auto_generated.data_a[5]
data_a[6] => altsyncram_aqb1:auto_generated.data_a[6]
data_a[7] => altsyncram_aqb1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_aqb1:auto_generated.address_a[0]
address_a[1] => altsyncram_aqb1:auto_generated.address_a[1]
address_a[2] => altsyncram_aqb1:auto_generated.address_a[2]
address_a[3] => altsyncram_aqb1:auto_generated.address_a[3]
address_a[4] => altsyncram_aqb1:auto_generated.address_a[4]
address_a[5] => altsyncram_aqb1:auto_generated.address_a[5]
address_a[6] => altsyncram_aqb1:auto_generated.address_a[6]
address_a[7] => altsyncram_aqb1:auto_generated.address_a[7]
address_a[8] => altsyncram_aqb1:auto_generated.address_a[8]
address_a[9] => altsyncram_aqb1:auto_generated.address_a[9]
address_b[0] => altsyncram_aqb1:auto_generated.address_b[0]
address_b[1] => altsyncram_aqb1:auto_generated.address_b[1]
address_b[2] => altsyncram_aqb1:auto_generated.address_b[2]
address_b[3] => altsyncram_aqb1:auto_generated.address_b[3]
address_b[4] => altsyncram_aqb1:auto_generated.address_b[4]
address_b[5] => altsyncram_aqb1:auto_generated.address_b[5]
address_b[6] => altsyncram_aqb1:auto_generated.address_b[6]
address_b[7] => altsyncram_aqb1:auto_generated.address_b[7]
address_b[8] => altsyncram_aqb1:auto_generated.address_b[8]
address_b[9] => altsyncram_aqb1:auto_generated.address_b[9]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_aqb1:auto_generated.clock0
clock1 => altsyncram_aqb1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_aqb1:auto_generated.q_b[0]
q_b[1] <= altsyncram_aqb1:auto_generated.q_b[1]
q_b[2] <= altsyncram_aqb1:auto_generated.q_b[2]
q_b[3] <= altsyncram_aqb1:auto_generated.q_b[3]
q_b[4] <= altsyncram_aqb1:auto_generated.q_b[4]
q_b[5] <= altsyncram_aqb1:auto_generated.q_b[5]
q_b[6] <= altsyncram_aqb1:auto_generated.q_b[6]
q_b[7] <= altsyncram_aqb1:auto_generated.q_b[7]


|core_1c6|RAM_1K:inst17|altsyncram:altsyncram_component|altsyncram_aqb1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7